Abstract: The present invention relates generally to the fields of semiconductor lithography. More particularly, it concerns methods, compositions, and apparatuses relating to 157 nm and 193 nm soft pellicles and the use of perfluorinated polymers in the creation of pellicles.

Abstract: Methods and apparatuses for cleaning a surface is provided. In one embodiment, a method includes the step of determining the type and size of the contaminant particles. A solution, which may include a plurality of variable size particles, may be selected such that an appropriate size cleaning particle is used during the cleaning process. The solution may include polystyrene latex particles or other cleaning particles. Alternatively, the solution may be a slurry. The solution and particles are delivered to the surface via a nozzle at a velocity that does not damage the surface and that clears the contaminants from the surface.

Abstract: Methods for characterizing a semiconductor material using optical metrology are disclosed. In one respect, a electromagnetic radiation source may be directed in a direction substantially parallel to patterns on a semiconductor material. A polarized spectroscopic reflectivity may be obtained, and a critical point data may be determined. Using the critical point data, physical dimensions of the patterns may be determined. In other respects, using optical metrology techniques, a critical point data relating to electron mobility may be determined.

Abstract: Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques may be used to define the gate stack.

Abstract: Filters for EUV lithography, methods of manufacture thereof, and methods of filtering in an EUV lithography system are disclosed. The filter comprises a nanotube material layer sandwiched by two thin material layers that are highly transmissive and provide structural support for the nanotube material layer. The filter is supported on at least one side by a patterned structural support. The filter mitigates debris, provides spectral purity filtering, or both.

Abstract: Apparatus and method for a substantially distortion free immersion lithography is provided. The apparatus includes a lens element, an outlet for drawing immersion fluid towards the lens element, and a collector ring coupled to the central outlet for removing the immersion fluid. The method includes positioning a lens element relative to a wafer to provide a space between the lens element and wafer, introducing immersion fluid to that space, and drawing the immersion fluid from that space to minimize gas bubbles in the immersion fluid, and repeating the introducing and drawing steps to maintain the flow of the immersion fluid during a lithography process.

Abstract: A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.di-elect cons. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

Abstract: A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer.

Abstract: An apparatus for rapid thermal processing of silicon wafers is provided. The apparatus may include a heating element, sensing element and a cooling element, all of which are positioned in opposing relation to a backside of a silicon wafer. A method of using the apparatus includes using the apparatus to rapidly heat a wafer, apply desired processing assists, and rapidly cool the wafer. The apparatus may also include an array of sensing elements which are interposed between heating elements. The sensing elements may be a combination of absolute and relative sensors. The array permits accurate zonal control of the heating elements and prevents cross talk between the heaters. The apparatus may be used to monitor the temperature at various points across a wafer and to control the associated heating elements in response to the monitoring step. The apparatus may also include a high speed rotating support for the wafer.

Abstract: Buffered slurries are used in a semiconductor process for chemical mechanical polishing of metal layers, such as aluminum or titanium. The slurries may comprise an oxidant capable of causing a passive oxide film to form on a metal based layer. The oxidant may comprise a diluent and may be optionally formulated with a separate oxidizing agent, such as ammonium peroxydisulfate. The slurries may include a buffer that maintains a slurry pH where the passive metal oxide film is stable. This pH may be between about 4 and about 9.

Abstract: An RF sensor having a novel current sensing probe and a voltage sensing probe to measure voltage and current. The current sensor is disposed in a transmission line to link all of the flux generated by the flowing current in order to obtain an accurate measurement. The voltage sensor is a flat plate which operates as a capacitive plate to sense voltage on a center conductor of the transmission line, in which the measured voltage is obtained across a resistance leg of a R-C differentiator circuit formed by the characteristic impedance of a connecting transmission line and a capacitance of the plate, which is positioned proximal to the center conductor.

Abstract: Chemical mechanical polishing slurry characteristics, such as oxidant concentration and abrasive particle dispersion, are determined using electrochemical measurement techniques, such as chronoamperometry, amperometry, chronopotentiometry, ionic conductivity, or linear sweep potentiometry. Slurry characteristics may be tested and monitored independent of a CMP polishing tool. Slurry characteristics may also be automatically controlled in an on-line chemical mechanical polishing process using electrochemical measurements.

Abstract: There is described a slurry for use in chemical mechanical polishing of copper layers in integrated circuit fabrication. The slurry includes a chromate oxidant, such as sodium chromate tetrahydrate (Na.sub.2 CrO.sub.4.4H.sub.2 O). The chromate oxidant provides a slightly basic slurry solution that enhances removal characteristics for copper layers. In one embodiment, the slurry has a pH between about 6 and about 9.

Abstract: An RF sensor having a novel current sensing probe and a voltage sensing probe to measure voltage and current. The current sensor is disposed in a transmission line to link all of the flux generated by the flowing current in order to obtain an accurate measurement. The voltage sensor is a flat plate which operates as a capacitive plate to sense voltage on a center conductor of the transmission line, in which the measured voltage is obtained across a resistance leg of a R-C differentiator circuit formed by the characteristic impedance of a connecting transmission line and a capacitance of the plate, which is positioned proximal to the center conductor.

Abstract: An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.

Abstract: A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled.

Abstract: A forced-flow polishing technique forcibly flows slurry across the surface of a wafer. The slurry and the wafer are contained in a confined space so that the slurry flow is between a fixed upper and lower boundaries. The slurry flow places selective stress on wafer features such that taller surfaces are eroded at a faster rate. The constant flow allows for uniformity in achieving the selective erosion across the wafer surface.

Abstract: The present invention discloses a saturable reactor and a method for decoupling the interwinding capacitance from the frequency limitations of the reactor so that the equivalent electrical circuit of the saturable reactor comprises a variable inductor. The saturable reactor comprises a plurality of physically symmetrical magnetic cores with closed loop magnetic paths and a novel method of wiring a control winding and a RF winding. The present invention additionally discloses a matching network and method for matching the impedances of a RF generator to a load. The matching network comprises a matching transformer and a saturable reactor.

Abstract: A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.