Patents Assigned to Semiconductor Manufacturing (Shanghai) International Corporation
  • Patent number: 11145756
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are disclosed. A forming method may include: providing a base, including a first region used to form a well region and a second region used to form a drift region, where the first region is adjacent to the second region; and patterning the base, to form a substrate and fins protruding out of the substrate, where the fins include first fins located at a junction of the first region and the second region and second fins located on the second region, where the quantity of the second fins is greater than the quantity of the first fins. In some implementations of the present disclosure, the quantity of the second fins is increased to correspondingly increase the length of a flow path in which a current flows from a drain region to a source region, thereby reducing a voltage drop in the current flow path, and further improving a breakdown voltage of an LDMOS, to improve the device performance of the LDMOS.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 12, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Fei Zhou
  • Patent number: 11121313
    Abstract: A semiconductor structure and a formation method thereof are disclosed. The formation method includes: providing a base; forming a dielectric layer on the base; forming a conductive via running through the dielectric layer; forming a conductive plug in the conductive via; forming a protective layer on the dielectric layer, wherein the protective layer covers the conductive plug; forming an aligner trench in the protective layer and the dielectric layer, wherein the aligner trench is isolated from the conductive plug; after forming the aligner trench, removing the protective layer to expose a top portion of the conductive plug; and after removing the protective layer, forming a magnetic tunnel junction (MTJ) laminated structure on the conductive plug.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 14, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Huan Liu
  • Patent number: 11121252
    Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 14, 2021
    Assignees: Semiconductor Manufacturing (Beijing) Intel Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
  • Patent number: 11114548
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor devices and manufacturing methods for the same. A semiconductor device may include: a substrate; a first active region on the substrate; a first gate structure positioned on the first active region; and a first source and a first drain that are positioned in the first active region and respectively on two sides of the first gate structure, where a size of the first drain is larger than a size of the first source. In forms of the present disclosure, because the size of the first drain is larger than the size of the first source, a current from the first drain to the first source is greater than a current from the first source to the first drain, so that the semiconductor device can make a read current relatively low and a write current relatively high in a static random access memory (SRAM), thereby improving a read margin and a write margin.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: September 7, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhenghao Gan, Junhong Feng
  • Patent number: 11075287
    Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. In one form, a method for forming a semiconductor structure includes: providing a base; forming multiple spaced filling layers in the base; etching the base to form multiple independent fin portions; and etching the filling layers to form multiple independent pseudofin portions. In one form a semiconductor structure of the present disclosure includes: a substrate, multiple independent fin portions and multiple independent pseudofin portions, wherein the substrate includes device areas, and isolating areas located between the device areas; the multiple independent fin portions are located on the substrate in the device areas and are the same with the substrate in material; and the multiple independent pseudofin portions are located on the substrate in the isolating areas and are different from the substrate in material.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Nan Wang, Ruoyuan Li
  • Patent number: 11075270
    Abstract: The present disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a base, the base including a source-drain doped region and an interlayer dielectric layer over the source-drain doped region; etching the interlayer dielectric layer to form an opening that exposes the source-drain doped region; and forming a first doped region at the top of the source-drain doped region exposed by the opening and a second doped region over the first doped region, a projection of the second doped region on the base covering a projection of the first doped region on the base, the doping ion types of the first doped region, the second doped region and the source-drain doped region being the same, and the ion doping concentration of the first doped region and the second doped region being higher than the ion doping concentration of the source-drain doped region.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Zhaomeng
  • Patent number: 11075284
    Abstract: A semiconductor structure and a forming method thereof are provided. One form of the forming method includes: providing a base, where a well region and a drift region adjacent to the well region are formed in the base; forming a trench in the drift region; forming a diffusion barrier layer in the trench; after the diffusion barrier layer is formed, forming a gate structure on the base at a junction between the well region and the drift region, where the gate structure is located on a side of the diffusion barrier layer near the well region; and forming a source region in the well region on one side of the gate structure, and forming a drain region in the drift region on the other side of the gate structure, where the drain region is located on a side of the diffusion barrier layer in the drift region away from the well region.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Zhaomeng
  • Patent number: 11075135
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are disclosed. A form of a method for forming a semiconductor structure includes: providing a base; patterning the base, to form a substrate and fins protruding out of the substrate, where each fin includes a bottom fin and a top fin located on the bottom fin, and in a direction perpendicular to an extension direction of each fin, a width of the top fin is less than a width of the bottom fin; and forming an isolation structure on the substrate exposed by a fin, where the isolation structure covers at least a sidewall of the bottom fin, and a top of the isolation structure is lower than a top of the fin.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 27, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Fei Zhou
  • Patent number: 11069792
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 20, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Patent number: 11069694
    Abstract: A semiconductor structure and a method for forming same are provided. In one form a method includes: providing a substrate with a discrete first gate laminated structure formed on the substrate; forming, on a portion of the substrate exposed from the first gate laminated structure, a unit dielectric layer covering a portion of a side wall of the first gate laminated structure, where the first gate laminated structure and the unit dielectric layer enclose a unit groove; forming an isolation spacer layer on a side wall of the unit groove, where the isolation spacer layer is in contact with the unit dielectric layer; forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and annealing the metal layer to form a metal silicide layer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: July 20, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Han Liang, Wang Hai Ying
  • Patent number: 11062952
    Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The forming method includes forming sacrificial layers and spacer on a dielectric layer, wherein the sacrificial layers and the spacer cover the dielectric layer at the top of a gate and expose the dielectric layer on at least part of source-drain doping layers, the sacrificial layers include the first sacrificial layer located on the dielectric layer at the top of the gate, and side walls of the first sacrificial layer are provided with the spacer; after the sacrificial layers and the spacer is formed, the first sacrificial layer is removed; and the dielectric layer is etched with a patterning layer as a mask, and a first contact hole and second contact holes are formed in the dielectric layer. The embodiments and implementations of the present disclosure can avoid double graphics of the dielectric layer and the alignment error.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: July 13, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Patent number: 11063119
    Abstract: Disclosed are a semiconductor structure and a method for forming same.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 13, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Patent number: 11011412
    Abstract: A semiconductor structure and a method for forming same are provided.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Wei Shi, Youcun Hu, Xiamei Tang
  • Patent number: 11011608
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Jin Jisong
  • Patent number: 11011416
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Jin Jisong
  • Patent number: 11011627
    Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a device region for forming devices and isolation regions located on two sides of the device region; patterning the base to form a substrate and fins protruding from the substrate; forming, on two sides of the device region, first dummy fins protruding from the substrate of the isolation region; and forming an isolation layer on the substrate exposed by the fins and the first dummy fins, where the isolation layer covers a part of side walls of the fin. In some implementations of the present disclosure, the setting of the first dummy fins improves the uniformity of pattern density in peripheral regions for each fin, which is advantageous for improving the thickness uniformity of an isolation layer in the device region, reducing the probability that the fin is bent or tilted, and improving electrical properties of the semiconductor structure.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Patent number: 10998396
    Abstract: A semiconductor structure and a forming method thereof are disclosed. The forming method includes: providing a base; forming a first electrode layer on the base; forming a capacitance dielectric layer on a top and a sidewall of the first electrode layer; and forming a second electrode layer conformally covering the capacitance dielectric layer. Compared with a solution in which the capacitance dielectric layer only covers the top of the first electrode layer, in the present disclosure, an effective area between the second electrode layer and the first electrode layer is increased, the second electrode layer, the first electrode layer, and the capacitance dielectric layer located on the top of the first electrode layer construct one capacitance, and the second electrode layer, the first electrode layer, and the capacitance dielectric layer located on the sidewall of the first electrode layer construct other four capacitances. That is, the formed capacitor structure includes five parallel capacitances.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 4, 2021
    Assignees: Semiconductor Manufacturing (Beijing) international Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Hu Lianfeng, Hu Youcun, Yang Ming, Bei Duohui, Ni Baibing
  • Patent number: 10991596
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Jin Jisong
  • Patent number: 10991690
    Abstract: A semiconductor structure and a method for forming same are provided. The forming method includes: providing a substrate, a fin protruding from the substrate, and at least two channel laminates sequentially located on the fin, where each channel laminate includes a sacrificial layer and a channel layer; forming a gate structure across the channel laminates; forming, in the channel laminates, a groove that exposes the fin, where after the groove is formed, the fin, the channel layer adjacent to the fin, and the remaining sacrificial layer encircle a first trench, adjacent channel layers and the remaining sacrificial layer between the adjacent channel layers encircle a second trench; forming first spacers in the first trench and the second trench; and forming a source-drain doping layer in the groove.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Patent number: 10990000
    Abstract: The present disclosure teaches a photolithography plate and a mask correction method, and relates to the field of semiconductor technologies. In forms of the mask correction method, a patterned mask is formed on a substrate, a location of a scattering bar embedded in the substrate is determined according to the mask, and an opening is formed at the determined location so as to embed the scattering bar in the opening. A scattering bar is embedded in a substrate of a photolithography plate so as to effectively avoid the impact of the scattering bar on a mask pattern, reduce a deposition loss, improve the correction effect, and shorten a correction time.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Jiancheng Zhang, Wei Wu, Chenbo Zhang