Patents Assigned to SGS Microelettronica S.p.A.
  • Patent number: 4764692
    Abstract: An N-channel power switch is controllable through two inputs by typical control signals for N-channel and P-channel MOS transistors. In the first case the control signal is brought back with unchanged polarity on the gate of the power switch which consequently operates in the peculiar manner of an N-channel device. In the second case the control signal charges a capacitor which reproduces on the gate of the power switch the same operating condition, causing it to operate again as an N-channel device although with P-type control.
    Type: Grant
    Filed: September 18, 1986
    Date of Patent: August 16, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Gianpietro Bellinvia, Giuseppe Faini
  • Patent number: 4752702
    Abstract: A bootstrap condenser connected to the output of the circuit is preloaded during the low output state when the load transistor is off and the drive transistor is normally on. A commutation signal brings about extinction of the drive transistor and connection of the condenser to the gate of the load transistor to turn on the latter and secure the resulting rise of the circuit output. Transistors of the pilot circuit are arranged for maximum bootstrap efficiency.
    Type: Grant
    Filed: July 31, 1986
    Date of Patent: June 21, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Maurizio Gaibotti
  • Patent number: 4752722
    Abstract: An amplifier stage with variable gain dependent on the anode voltage is interposed between a ramp generator having constant amplitude ramp output voltage and the vertical deflection stage in such a manner as to vary the input voltage of said vertical deflection stage in accordance with anode voltage variations. In such a manner the vertical deflection current varies correspondingly.
    Type: Grant
    Filed: March 4, 1986
    Date of Patent: June 21, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Pietro Erratico, Mauro Merlo, Silvano Coccetti
  • Patent number: 4746871
    Abstract: A differential switched capacitor type integrator, particularly useful for building analog sampled-data switched capacitor filters, utilizes a single integration capacitor (or array of unitary capacitors connected in parallel) instead of the two distinct integration capacitors required in the known differential integrators. The number of the required capacitors is therefore reduced to one half in comparison to that required in accordance with the prior art.
    Type: Grant
    Filed: October 15, 1986
    Date of Patent: May 24, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Alejandro de la Plaza
  • Patent number: 4740821
    Abstract: Described is an improved NPN equivalent structure with a breakdown voltage higher than the intrinsic breakdown voltage of the NPN transistor utilizing a complementary PNP transistor and a JFET transistor with the gate connected to ground, the drain connected to the base of the PNP and the source connected to the collectors of the complementary pair. An integrated form of the structure is particularly advantageous and the equivalent NPN transistor is substantially exempt from Early effect and has improved output current capacity.
    Type: Grant
    Filed: March 5, 1987
    Date of Patent: April 26, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Franco Bertotti, Maurizio Zuffada, Paolo Ferrari
  • Patent number: 4739378
    Abstract: Described is an integrated semiconductor structure for the protection from electrical discharges of electrostatic origin of particularly sensitive components of an integrated circuit. The structure is almost entirely formed directly underneath a particular input pad thus requiring a minimum useful area and is characterized by very high damaging voltage and speed of intervention because of the extremely low series resistance of the two zener junctions constituting the structure.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: April 19, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Paolo Ferrari, Franco Bertotti
  • Patent number: 4739228
    Abstract: A variable-gain rectifier-amplifier with regulated voltage converts the output ramp of a ramp generator with regulating resistance of ramp amplitude into a triangular wave form with adjustable linearity which a feedback circuit brings back to said regulating resistance in the form of alternating current superimposing it on the direct current regulated through said resistance. This provides an S correction of the output ramp which depends on the gain regulation voltage of the rectifier-amplifier circuit.
    Type: Grant
    Filed: May 16, 1986
    Date of Patent: April 19, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Roberto Viscardi, Silvano Coccetti, Silvano Gornati
  • Patent number: 4733196
    Abstract: A current gain stage with low voltage drop usable in place of a Darlington's current gain stage is described. This stage maintains the precision characteristics of the output current value, though presenting a lower voltage drop. The stage is formed by connecting the collector of the input transistor (driver) to a current mirror, the output current of which is added to the output current of the gain stage for maintaining the high precision.
    Type: Grant
    Filed: December 4, 1986
    Date of Patent: March 22, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Pietro Menniti, Antonella Lanati
  • Patent number: 4727465
    Abstract: This circuit, for reliably driving a load both in DC and AC mode with a low dissipation, comprises a pair of MOS power transistors, in a push-pull configuration, and a bootstrap circuit including a bootstrap capacitor placed between the source of the upper MOS transistor and a reference voltage point, through a first switch. A second switch is arranged between the supply line and the gate of the upper MOS transistor, while a third switch is arranged between the gate of the upper MOS transistor and the point common to the first switch and the bootstrap capacitor. During DC operation, the switches are open or closed in order to allow for the connection of the gate of the MOS power transistor to the supply voltage. During AC operation, the switches are controlled thereby, alternately the capacitor is charged at the voltage of the reference voltage point and the upper MOS transistor is held at a gate-to-source voltage sufficient to feed the load.
    Type: Grant
    Filed: August 18, 1986
    Date of Patent: February 23, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Carlo Cini, Claudio Diazzi, Domenico Rossi
  • Patent number: 4725769
    Abstract: The switching driving device with current limitation, operating reliably even with high switching frequencies, comprises a drive stage receiving at the input a timing clock signal at a preset frequency and generating at the output a drive signal synchronized with the timing clock signal, a power element connected at the input to the drive stage, receiving therefrom the drive signal and generating a load supply signal, a load fed by the power element, and a current sensor generating an overload signal when the current in the load has reached a preset threshold. The current limitation is obtained through a memory element connected to the current sensor and disabling the drive stage in the presence of the overload signal. In order to obtain a reliable operation, in the presence of the overload signal the drive stage is controlled at a switching frequency which is lower than the preset frequency of the timing clock signal.
    Type: Grant
    Filed: April 9, 1987
    Date of Patent: February 16, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Carlo Cini, Claudio Diazzi, Giuseppe Gattavari
  • Patent number: 4725810
    Abstract: This method of making an implanted resistor comprises the steps of implanting the resistor with ordinary techniques and deposition over the implanted resistor of a polysilicon layer having a set thickness and fully covering the resistor. Thus, the resulting resistor is unaffected by any subsequent thermal treatments and its value remains constant irrespective of any high potential metal layers or connections crossing it. The method affords in particular resistive values of the order of 1 kOhms/square.
    Type: Grant
    Filed: June 20, 1986
    Date of Patent: February 16, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Mario Foroni, Paolo Ferrari, Franco Bertotti
  • Patent number: 4721686
    Abstract: This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant on the surface of an epitaxial layer, without masking, and arsenic implant in predetermined locations of the epitaxial layer surface by means of an appropriate mask. A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms, but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N.sup.+ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted.
    Type: Grant
    Filed: January 22, 1987
    Date of Patent: January 26, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Claudio Contiero, Paola Galbiati, Antonio Andreini
  • Patent number: 4720641
    Abstract: With a MOS power element is associated at least one CMOS pilot circuit supplied by a condenser charged with a voltage taken from the power circuit during the interdiction phases of the power element. The entire device is preferably enclosed in a single monolithic chip except for the condenser which remains outside.
    Type: Grant
    Filed: June 10, 1986
    Date of Patent: January 19, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Giuseppe Faini
  • Patent number: 4718977
    Abstract: Structure and method for metallization patterns of different thicknesses on a semiconductor device or integrated circuit. The improved structure and method utilizes three layers of metal in order to reduce the required number of processing steps. One preferred embodiment entails a single metal deposition sequence followed by two etch steps, while a second embodiment, suitable for thicker metallization, requires only two depositions and two etch steps.
    Type: Grant
    Filed: September 6, 1985
    Date of Patent: January 12, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Claudio Contiero, Giulio Iannuzzi, Giorgio De Santi, Fabrizio Andreani
  • Patent number: 4719184
    Abstract: After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: January 12, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Daniele Cantarelli, Giuseppe Crisenza, Pierangelo Pansana
  • Patent number: 4716321
    Abstract: A low noise, high thermal stability attenuator of the integratable type is disclosed. The attenuator comprises a fixed network of resistive elements, having a plurality of outputs each at a different attenuation level, and a switched amplifier receiving at its input such different attenuation outputs, as well as a control signal which specifies which of the amplifier inputs is to be output. Advantageously, this attenuator may be implemented in several stages, each having different attenuation ranges or steps.
    Type: Grant
    Filed: February 10, 1986
    Date of Patent: December 29, 1987
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Pietro Erratico
  • Patent number: 4714898
    Abstract: A device is disclosed for protecting against shorts the transistors of the push-pull stage in a power amplifier operating on a low voltage supply, in particular for car radio sets. The device comprises sensors which are responsive to currents flowing through the two transistors which form the amplifier push-pull stage, and current-to-voltage converters which convert the sensed currents into corresponding respective voltage signals. The latter are compared in respective voltage-comparing circuits with a reference voltage indicative of the highest admissible current through either of the transistors while the other is shorted. The device also comprises two additional voltage comparators wherein the voltage applied to the load, which may be of a resistive or a reactive type, is compared with a set reference voltage which is lower than or in the extreme equal to, in absolute value, the voltage supply to the amplifier push-pull stage.
    Type: Grant
    Filed: June 6, 1986
    Date of Patent: December 22, 1987
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Edoardo Botti, Fabrizio Stefani
  • Patent number: 4704738
    Abstract: The input stage of a radio receiver incudes a differential amplifier circuit, whose gain is adjusted by a voltage generated by an AGC circuit, and a mixer circuit. An attenuator stage with a predetermined attenuation coefficient is coupled between the input terminal of differential circuit and the input terminal of the mixer circuit. When the level of the input signal increases beyond a given value, the differential amplifier circuit is deactivated and the signal reaches the mixer circuit through the attenuator stage.
    Type: Grant
    Filed: October 1, 1984
    Date of Patent: November 3, 1987
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Rinaldo Graziadei, Michaelango Lorusso
  • Patent number: 4703552
    Abstract: The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.
    Type: Grant
    Filed: January 9, 1985
    Date of Patent: November 3, 1987
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Livio Baldi, Giuseppe Corda, Giulio Iannuzzi, Danilo Re, Giorgio De Santi
  • Patent number: 4703249
    Abstract: A stabilized generator includes an operational amplifier with capacitive negative feedback whose output signal controls a current regulator which drives the input of a current mirror circuit, the mirrored current from the mirror circuit controlling a feedback circuit adapted to drive the operational amplifier in order to maintain the mirrored current constant.
    Type: Grant
    Filed: July 28, 1986
    Date of Patent: October 27, 1987
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Alejandro De La Plaza, Guido Torelli