Patents Assigned to Sharp Kabushiki Kaisha
  • Patent number: 11917858
    Abstract: The display device includes a light-emitting element layer provided with a plurality of light-emitting elements, and a TFT layer that is provided below the light-emitting element layer and includes TFT configured to drive the plurality of light-emitting elements. Further, at least one thermal insulation layer configured to thermally insulate the plurality of light-emitting elements from external heat is provided, and the thermal insulation layer includes a molybdenum-containing complex and a polyphenylene sulfide-based resin.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 27, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masanobu Mizusaki
  • Patent number: 11917110
    Abstract: An image processing apparatus including: a job executor; a storage that stores therein history information related to execution of jobs; and a controller that sets a display priority of the history information based on an operation mode of the job executor when calling up the history information.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: February 27, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Mayuko Yoshida, Kumiko Ogino
  • Patent number: 11908408
    Abstract: Provided is a display device with pixel circuits, each including first compensation transistor connected to a control terminal of a drive transistor at one conductive terminal, an intermediate node at another conductive terminal, and a scanning line at a control terminal, a second compensation transistor connected to the intermediate node at one conductive terminal, a conductive terminal of the drive transistor at another conductive terminal, and the scanning line at a control terminal, and a capacitor connected to the intermediate node at one electrode and a control line at another electrode. The driver circuit changes a potential of the scanning line from on to off level and also changes a potential of the control line from a second level to a first level, in an opposite direction to the change in the potential thereof.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tomoo Furukawa
  • Patent number: 11908217
    Abstract: A document reading device includes a document conveyer, a first reader reading, in a first reading position, a first surface of a conveyed document such that a read area is larger than the conveyed document, a second reader reading, in a second reading position, a surface (second surface) opposite to the first surface such that a read area is larger than the conveyed document, a region detector executing a process of detecting a first document region that is a region of a document in first document image data and a process of detecting a second document region that is a region of the document in second document image data, and a cropping processor cropping a document portion on the first surface as first cropped image data and cropping a document portion on the second surface as second cropped image data, based on one of the document regions successfully detected.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kazuma Ogawa
  • Patent number: 11910384
    Abstract: A terminal apparatus includes a receiver configured to monitor a PDCCH with a DCI format on an active downlink BWP in a serving cell in a Secondary Cell Group (SCG), the DCI format being used for scheduling a PDSCH, and receive the PDSCH on the downlink BWP, and a transmitter configured to transmit a HARQ-ACK on a PUCCH.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tomoki Yoshimura, Shoichi Suzuki, Toshizo Nogami, Wataru Ouchi, Taewoo Lee, Huifa Lin
  • Patent number: 11910464
    Abstract: A terminal apparatus that communicates with one or multiple base station apparatuses includes: a receiver configured to receive an RRC connection reconfiguration message including a DRB configuration from a base station apparatus of the one or multiple base station apparatuses; and a processing unit configured to associate an DRB that is established with an EPS bearer identity included in information of a DRB configuration in a case that information indicating that a full configuration is applied is included in the RRC connection reconfiguration message received by the receiver, a DRB identity included in the information of the DRB configuration is not present in a part of a current configuration of the terminal apparatus, and an LTE PDCP entity is established in the DRB that is established and has the DRB identity.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takako Hori, Shohei Yamada, Hidekazu Tsuboi
  • Patent number: 11908873
    Abstract: An active matrix substrate including a resin substrate including a plurality of external connection terminals arranged near a display region, the active matrix substrate includes: a plurality of first lead wires each extending from one of the external connection terminals to the display region; and a plurality of second lead wires each extending from one of the external connection terminals to a separation line, the second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the second lead wires being greater than an arrangement pitch of the first lead wires.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinji Ichikawa, Shinsuke Saida, Shoji Okazaki, Tokuo Yoshida, Hiroki Taniyama, Kohji Ariga, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada, Yoshihiro Kohara, Koji Tanimura
  • Patent number: 11910671
    Abstract: With respect to a display device having an external compensation function, a monitor time can be shortened without increasing the number of wiring lines. A pixel circuit in an i-th row and a j-th column includes an organic EL element (display element), a writing control transistor, a drive transistor, a monitor control transistor, and a holding capacitor. A control terminal of the drive transistor is connected to a data signal line S(j) in the j-th column via the write control transistor. The monitor control transistor includes a first conduction terminal connected to a second conduction terminal of the drive transistor, and a second conduction terminal connected to a data signal line S(j+1) in a (j+1)-th column.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Yamamoto, Kohhei Tanaka, Takayuki Nishiyama
  • Patent number: 11910417
    Abstract: A terminal apparatus of the present invention receives setting of an initial DL BWP by using an RRC message, the setting of the initial DL BWP comprises setting a first parameter and a second parameter of a CORESET #0, a value of an identifier of the CORESET #0 is 0, the first parameter represents the size of the CORESET #0, and the second parameter represents the size of the initial DL BWP. The terminal apparatus of the present invention receives a DCI format that schedules a PDSCH in an active DL BWP, and identifies, based on a field in the DCI format, a resource block set to which the PDSCH is allocated. A value of the field is determined based on the size of the DL BWP, the start resource block, and the number of consecutively allocated resource blocks. The size of the DCI format in a USS is determined based on the size of the CORESET #0, and when the field is applied to the active DL BWP, the size of the DL BWP is the size of the CORESET #0.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 20, 2024
    Assignees: SHARP KABUSHIKI KAISHA, FG Innovation Company Limited
    Inventors: Liqing Liu, Shohei Yamada, Hiroki Takahashi, Masayuki Hoshino, Hidekazu Tsuboi
  • Patent number: 11908361
    Abstract: The display device is provided with a degree-of-degradation calculating circuit that determines a degree of degradation representing a level of degradation of a compensation-target circuit element included in each of K pixel circuits which are some or all of a plurality of pixel circuits; a variation coefficient calculating circuit that calculates, as a variation coefficient, a value depending on a deviation determined based on degrees of degradation of the K pixel circuits; a reference luminance setting circuit that sets, based on the variation coefficient, reference luminance for determining display luminance of each display element after degradation compensation; and a compensation computing circuit that compensates for degradation of the compensation-target circuit elements by correcting input video signals based on the reference luminance and the degree of degradation of each of the K pixel circuits, upon generating video signals to be supplied to the plurality of pixel circuits.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroyuki Furukawa, Chie Toridono, Masafumi Ueno
  • Patent number: 11909936
    Abstract: An image forming apparatus records identification information of an external memory and identification information of a scan job as a log when the external memory is attached to start the scan job. When the external memory is removed in the middle of the scan job, scan data is temporarily saved together with the identification information of the job. When the removed external memory is attached, for example, in a ready state, log data is referred to determine whether the external memory is that removed in the middle of the job and whether the scan data associated with the external memory is saved. When it is determined that the scan data is saved, the scan data is saved in the external memory.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hiroyuki Ishikura
  • Patent number: 11909680
    Abstract: To provide a terminal apparatus and a communication method capable of improving reliability and frequency efficiency in a case of transmission by beamforming. Provided are a higher layer processing unit configured with demodulation reference signal (DMRS) antenna port groups for indicating two groups of antenna ports of a DMRS, a receiver configured to receive the DMRS, downlink control information (DCI), and a downlink shared channel (PDSCH), and a decoding unit configured to decode the PDSCH, wherein the PDSCH includes a transport block, and in a case that the number of the transport blocks configured in the DCI is one, the PDSCH demodulated using a DMRS of a first group and/or the PDSCH demodulated using a DMRS of a second group is used to decode one transport block.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryota Yamada, Hiromichi Tomeba, Hideo Namba, Yasuhiro Hamaguchi
  • Publication number: 20240057369
    Abstract: A light-emitting element includes: a cathode; an anode opposite the cathode; a light-emitting layer between the cathode and the anode; and an electron transport layer between the cathode and the light-emitting layer, the electron transport layer containing either a compound containing a Group IIB element, a Group IVB element, and elemental nitrogen or a compound containing the Group IVB element, a Group VIB element, and elemental boron.
    Type: Application
    Filed: January 13, 2021
    Publication date: February 15, 2024
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: YOSHIHIRO UETA
  • Patent number: 11903239
    Abstract: A display device includes the following: a base substrate; a light-emitting element on the base substrate with a TFT layer interposed therebetween, the light-emitting element forming a display region; a sealing film covering the light-emitting element and having a stack of, in sequence, first and second inorganic insulating films; a frame region surrounding the display region; a cut disposed in the frame region so as to partly cut the display region; a cut-peripheral wall disposed in the frame region between the display region and the cut, and extending along the boundary of the display region; an evaporated film between the cut-peripheral wall and the first inorganic insulating film; and an organic buffer layer disposed on a surface of the cut-peripheral wall and interposed between the first and second inorganic insulating films.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yoshifumi Ohta
  • Patent number: 11899397
    Abstract: The peak top molecular weight of the tetrahydrofuran-soluble component of the toner, as measured by gel permeation chromatography, is 4,000 or more and 6,500 or less. The tetrahydrofuran-insoluble component of the toner is 10% by weight or more and 30% by weight or less. When the endothermic peak temperature T1 in the heating process and the exothermic peak temperature T2 during the cooling process originating from the ester wax is measured using a differential scanning calorimeter, the value T1-T2 is 15° C. or more and 30° C. or less.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Osamu Wada, Yoritaka Tsubaki
  • Patent number: 11902546
    Abstract: This disclosure relates to video coding and more particularly to a method of decoding network abstraction layer (NAL) unit information. The method of decoding NAL unit information comprises: receiving a NAL unit header syntax structure having two bytes; and decoding a first 1-bit syntax element, a second 1-bit syntax element and a 6-bit syntax element in the NAL unit header syntax structure, wherein a value of the first 1-bit syntax element is equal to zero, a value of the second 1-bit syntax element is equal to zero, and the 6-bit syntax element specifies an identifier of a layer to which a VCL NAL unit belongs or an identifier of a layer to which a non-VCL NAL unit applies.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Sachin G. Deshpande
  • Patent number: 11902523
    Abstract: A video coding device may be configured to perform transform data coding according to one or more of the techniques described herein.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seung-Hwan Kim, Christopher Andrew Segall
  • Patent number: 11902479
    Abstract: A multi-function peripheral as an image processing device according to the present invention is wirelessly connected with a mobile terminal having a display and is capable of accepting an operation by a user via the mobile terminal. For this, a terminal side setting screen for operating the multi-function peripheral is displayed on the display of the mobile terminal. The terminal side setting screen includes buttons for an operation requiring the user to be in the vicinity of the multi-function peripheral. These buttons are brought in a mode capable of accepting the operation, when an estimated distance between the multi-function peripheral and the mobile terminal is less than or equal to a threshold value, whereas are brought in a mode incapable of accepting the operation, when the estimated distance exceeds the threshold value.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kayoko Seo
  • Patent number: 11900872
    Abstract: To make a frame size of a display device having an external compensation function smaller than those of the known display devices. Each of a plurality of unit circuits configuring a gate driver includes a first output control transistor including a second conduction terminal connected to a first output terminal-connected to another unit circuit and a control terminal connected to a first internal node, a second output control transistor including a second conduction terminal connected to a second output terminal configured to output an on level signal for at least a part of a monitoring period and a control terminal connected to a second internal node, and an output circuit control transistor including a first conduction terminal connected to the first internal node and a second conduction terminal connected to the second internal node. A potential to be applied to a control terminal of the output circuit control transistor is switched between a potential of a high level and a potential of a low level.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Ryo Yonebayashi
  • Patent number: 11903299
    Abstract: A TEG near the perimeter of a frame region is away from a TFT, which is disposed in a display region and is actually used for screen display. Hence, the characteristics of the TEG can change in a manner different from that in the characteristics of the TFT within the display region. Accordingly, provided is a display device that includes a TEG pattern disposed between the display region and a trench, and includes a dummy pixel circuit disposed between the display region and a barrier wall. The TEG pattern is outside the display region and is adjacent to at least the dummy pixel circuit.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Masahiko Miwa, Masaki Yamanaka, Yi Sun, Yohsuke Kanzaki, Seiji Kaneko