Patents Assigned to Shin-Etsu Handotai Co., Ltd.
  • Patent number: 10434621
    Abstract: A workpiece processing apparatus including a control unit that is provided with a storage medium on which a polishing load measured when an upper turn table is moved downward to a fixed position in a state wherein the workpiece is properly held in holding hole of the carrier is recorded in advance, calculates a difference between a polishing load measured when upper turn table is moved downward to the fixed position in a state wherein the workpiece is held in holding hole of the carrier and the polishing load recorded on the storage medium, and judges the occurrence of abnormal holding of the workpiece if the calculated difference exceeds a threshold value. As a result, it becomes possible to detect abnormal holding of a workpiece in a short time with a high degree of precision before the workpiece is processed and prevent breakages of the workpiece and the processing apparatus.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: October 8, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Taichi Yasuda, Tatsuo Enomoto
  • Publication number: 20190295883
    Abstract: A method for manufacturing an SOI wafer, including steps of: bonding a bond wafer and a base wafer each composed of a silicon wafer at room temperature with a silicon oxide film interposed therebetween; a thinning the bond wafer; and before the bonding step, cleaning the wafers with a hydrophilic cleaning liquid and drying the cleaned wafers by suction drying or spin drying. After the drying step is ended and before the bonding step is started, the wafers are stored until a state where a bonding speed at which the bonding step is to be performed is 20 mm/second or less. The bonding is performed with the bonding speed of 20 mm/second or less. This provides a method for manufacturing an SOI wafer by which an SOI wafer can be manufactured while generation of outer-peripheral micro voids is suppressed in a simple manner.
    Type: Application
    Filed: November 27, 2017
    Publication date: September 26, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Isao YOKOKAWA
  • Patent number: 10424484
    Abstract: Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: September 24, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Norihiro Kobayashi, Masatake Nakano
  • Patent number: 10414017
    Abstract: A polishing apparatus includes: a plurality of polishing heads for holding a wafer, a polishing pad for polishing the wafer, a rotatable turn table having the polishing pad attached thereto, a turn table driving mechanism for rotating the turn table, a plurality of wafer-detecting sensors for detecting coming off of the wafer from the polishing head during polishing, wherein the polishing apparatus has the wafer-detecting sensor disposed above peripheral portions of the respective polishing heads and on each downstream side in a rotation direction of the turn table with respect to the respective polishing heads. The polishing apparatus can detect coming off of a wafer from a polishing head during polishing more rapidly, and can prevent a breakage of the wafer thereby.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 17, 2019
    Assignees: SHIN-ETSU HANDOTAI CO., LTD., FUJIKOSHI MACHINERY CORP.
    Inventors: Junichi Ueno, Michito Sato, Kaoru Ishii, Hiromi Kishida, Yosuke Kanai, Yuya Nakanishi
  • Patent number: 10400353
    Abstract: A method controls a resistivity of a grown silicon single crystal by using a dopant when the silicon single crystal is grown by CZ method, including the steps of initially doping with a primary dopant such that the silicon single crystal has a predetermined conductive type and additionally doping with a secondary dopant having a conductive type opposite to that of the primary dopant continuously or intermittently, according to a solidification rate expressed by (crystalized weight)/(initial weight of silicon raw material) while growing the silicon single crystal, wherein in the additional doping step, the additional doping with the secondary dopant is carried out when the solidification rate is a predetermined value ? or more, while the crystal is not doped with the secondary dopant until the solidification rate reaches the predetermined value ?.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: September 3, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada, Kiyotaka Takano
  • Publication number: 20190267239
    Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.
    Type: Application
    Filed: July 3, 2017
    Publication date: August 29, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi OHTSUKI, Tadashi NAKASUGI, Hiroshi TAKENO, Katsuyoshi SUZUKI
  • Patent number: 10395933
    Abstract: A method for manufacturing a semiconductor wafer including: slicing off a plurality of wafers from an ingot; chamfering outer peripheral portions of the plurality of sliced wafers; and performing double-side polishing to polish both surfaces of each wafer whose outer peripheral portion is held by a carrier, wherein includes performing warp direction adjustment to uniform directions of warps of the plurality of wafers in one direction after the slicing and before the chamfering, and the chamfering and the double-side polishing are performed in a state where the directions of the warps of the plurality of wafers are uniformed in one direction after the warp direction adjustment. Consequently, it is possible to provide the method for manufacturing a semiconductor wafer which can suppress degradation of flatness of the double-side polished wafers even in case of uniforming the directions of the warps of the wafers in one direction before the double-side polishing.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: August 27, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yoshihiro Usami, Shiro Amagai
  • Patent number: 10388831
    Abstract: A light-emitting device including a window layer-cum-support substrate, a light-emitting portion provided on the window layer-cum-support substrate and including a second semiconductor layer of a second conductivity type, an active layer, and first semiconductor layer of a first conductivity type in stated order, a first ohmic electrode provided on the first semiconductor layer, and insulator top coat at least partially coating the first semiconductor layer surface and light-emitting portion side surface, wherein the first semiconductor layer surface and surface of the window layer-cum-support substrate are roughened, and the first semiconductor layer includes at least two layers of an active-layer-side layer and roughened-side layer, and roughened-side layer is formed of material having lower Al content than the active-layer-side layer.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 20, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Junya Ishizaki, Shogo Furuya
  • Patent number: 10365227
    Abstract: A detection device 1 includes an irradiator 3, a photodiode 4, and an evaluation portion 5. The irradiator 3 emits laser light to a surface of a substrate W. The light resulting from the laser light reflected at the surface of the substrate W is incident on the photodiode 4, and the photodiode 4 detects a first position P1 at which the light is incident. The evaluation portion 5 includes a calculation portion and a detection portion. The calculation portion calculates an inclination of the surface of the substrate W on the basis of the first position P1 and a second position P2 at which light is incident on the photodiode 4 when the laser light is reflected at the surface of the substrate W that is flat. The detection portion detects a defect formed on the surface of the substrate W on the basis of the inclination.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: July 30, 2019
    Assignees: SHIN-ETSU HANDOTAI CO., LTD., RAYRESEARCH CORPORATION
    Inventors: Tadao Kondo, Hisato Nakamura
  • Publication number: 20190228962
    Abstract: A method for manufacturing a silicon epitaxial wafer includes: preparing a test silicon wafer in advance, forming the multilayer film on a surface of the test silicon wafer, and measuring a warp direction and a warp amount (Warp) W of the silicon wafer having the multilayer film formed thereon; and selecting a silicon wafer as a device formation substrate and conditions for forming an epitaxial layer which is formed on the silicon wafer as the device formation substrate in such a manner that a warp which cancels out the measured warp amount W is formed in a direction opposite to the measured warp direction, and forming the epitaxial layer on a surface of the selected silicon wafer as the device formation substrate where the multilayer film is formed under the selected conditions for forming the epitaxial layer.
    Type: Application
    Filed: August 17, 2017
    Publication date: July 25, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Yasushi MIZUSAWA
  • Publication number: 20190221470
    Abstract: Method for manufacturing bonded SOI wafer by bonding bond wafer and base wafer each composed of silicon single crystal with insulator film being interposed therebetween, including steps of: depositing polycrystalline silicon layer on bonding surface side of base wafer; polishing surface of polycrystalline silicon layer to obtain polished surface; forming thermal oxide film on polished surface; forming insulator film on bonding surface of bond wafer; bonding step of bonding bond and base wafers by bringing insulator and oxide films into close contact with each other; and thinning bonded bond wafer to form SOI layer, wherein silicon single crystal wafer having resistivity of 100 ?·cm or more is used as base wafer, thermal oxide film formed on polished surface has thickness of 15 nm or more with RMS of 0.6 nm or less, and any heat treatment after bonding step is performed with maximum treatment temperature of 1150° C. or less.
    Type: Application
    Filed: April 25, 2017
    Publication date: July 18, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro KOBAYASHI, Hiroji AGA
  • Patent number: 10355092
    Abstract: A silicon epitaxial wafer including: a second intermediate epitaxial layer on a silicon substrate produced by being cut from a silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 3×1016 to 2×1017 atoms/cm3, a first intermediate epitaxial layer doped with a dopant, and an epitaxial layer of a device forming region stacked on the first intermediate epitaxial layer, and to a method of producing this wafer. Also providing an industrially excellent silicon epitaxial wafer that is produced with a silicon substrate doped with carbon and used as a semiconductor device substrate such as a memory, a logic, or a solid-state image sensor, and a method of producing this silicon epitaxial wafer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 16, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Masahiro Sakurada
  • Patent number: 10350788
    Abstract: Method for slicing a workpiece, including measuring a crystal axis orientation while holding a workpiece with a workpiece holder, setting the workpiece holder to a wire saw in such a manner that the measured crystal axis orientation is maintained, then adjusting a sliced plane orientation, pressing the workpiece against a wire row to slice the workpiece; the workpiece holder includes a portion slidable while holding the workpiece and a portion for fixing the slide portion, after measuring the crystal axis orientation, sliding the slide portion to move to the workpiece holder center in a manner that the measured crystal axis orientation is maintained, fixing the slide portion, setting the workpiece holder to the wire saw, then adjusting the sliced plane orientation, and slicing the workpiece. This enables an orientation measurement without limitation of distance between an orientation measuring instrument and plane to be measured can inhibit warpage deterioration and workpiece breakage.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: July 16, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Atsuo Uchiyama, Hisakazu Takano, Masahito Saitoh, Hirotoshi Kouzu
  • Publication number: 20190212384
    Abstract: A method for evaluating crystal defects by which a distribution of the crystal defects present in a silicon wafer is evaluated, includes forming an oxide film having a thickness equal to a crystal defect size to be evaluated on the silicon wafer, measuring GOI characteristics of the silicon wafer, and obtaining the distribution of the crystal defects having the crystal defect size to be evaluated in the silicon wafer from a measurement result of the GOI characteristics on a supposition that the crystal defects whose size is equivalent to the thickness of the oxide film are present in a region where the GOI characteristics are degraded. Consequently, the method for evaluating crystal defects by which a distribution of the crystal defects can be obtained even if a crystal defect size is 10 nm or less.
    Type: Application
    Filed: August 16, 2017
    Publication date: July 11, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Hisayuki SAITO
  • Patent number: 10347525
    Abstract: A method for producing a bonded SOI wafer, by ion implantation delamination to fabricate a bonded SOI wafer having a BOX layer and a SOI layer on a base wafer. After performing flattening heat treatment in an argon gas-containing atmosphere, sacrificial oxidation treatment adjusts the film thickness of the SOI layer, wherein the film thickness of the BOX layer is 500 nm or more. A sacrificial oxide film is formed so the relationship between the film thickness of the SOI layer on the sacrificial oxidation treatment is performed. The film thickness of the sacrificial oxide film formed by the sacrificial oxidation treatment satisfies 0.9d>t>0.45d. A method for producing a bonded SOI wafer can prevent the generation of particles from the outermost peripheral part, which is the form of an overhang by flattening heat treatment, of a SOI layer in the production of a bonded SOI wafer.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: July 9, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Isao Yokokawa
  • Patent number: 10345102
    Abstract: A method for evaluating warpage of a wafer, includes measuring the warpage of the wafer that is in a free state without suction and determining, from measured warpage data, a wafer warpage amount A between two points Q1 and Q2 and a wafer warpage amount B between two points R1 and R2, the points Q1 and Q2 being located on a straight line passing through an arbitrary point P in a wafer plane and a distance “a” away from the point P, the points R1 and R2 being located on the same straight line and a distance “b” away from the point P, the distance “b” differing from the distance “a”, calculating, from the wafer warpage amount A and the wafer warpage amount B, a difference in wafer warpage amount at the point P, and evaluating the warpage on the basis of the difference in wafer warpage amount.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: July 9, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Hisayuki Saito
  • Patent number: 10335918
    Abstract: A workpiece processing apparatus including: a center drum that is rotatable around a rotation axis and has at least one first groove formed in the axial direction on the peripheral surface, a carrier having a holding hole to insert and hold a workpiece to be processed, an upper and lower turn table that are rotatable around the rotation axis in a state wherein the carrier holding workpiece is interposed, at least one hook fitted in the upper turn table's internal circumference, with the tip being inserted into the first groove and movable along first groove; wherein the center drum has at least one second groove formed in the axial direction on peripheral surface, and second groove has a length different from that of the first groove and has a supporting surface to support the hook from below at a position above a position where upper turn table processes the workpiece.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 2, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Taichi Yasuda, Masanao Sasaki
  • Publication number: 20190198386
    Abstract: A method for manufacturing a bonded SOI wafer including a step of performing a heat treatment to each bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere to flatten a front surface of an SOI layer, wherein, at the time of performing the heat treatment in the argon atmosphere in a batch processing heat treatment furnace, a silicon wafer is arranged as a dummy wafer between the adjacent bonded SOI wafers housed in the batch processing heat treatment furnace to perform the heat treatment. Consequently, there is the method for manufacturing an SOI wafer which enables suppressing an increase in LPDs at the step of performing the heat treatment to a bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere in a batch processing heat treatment furnace to flatten a front surface of an SOI layer.
    Type: Application
    Filed: August 22, 2017
    Publication date: June 27, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru ISHIZUKA, Setsuya HAMA
  • Publication number: 20190181059
    Abstract: A method for evaluating surface defects of a substrate to be bonded: preparing a mirror-polished silicon single crystal substrate; inspecting surface defects on the mirror-polished silicon single crystal substrate; depositing a polycrystalline silicon layer on a surface of the silicon single crystal substrate subjected to the defect inspection; performing mirror edge polishing to the silicon single crystal substrate having the polycrystalline silicon layer deposited thereon; polishing a surface of the polycrystalline silicon layer; inspecting surface defects on the polished polycrystalline silicon layer; and comparing coordinates of defects detected at the step of inspecting the surface defects on the silicon single crystal substrate with counterparts detected at the step of inspecting the surface defects on the polycrystalline silicone layer and determining quality of the silicon single crystal substrate having the polycrystalline silicon layer as a substrate to be bonded on the basis of presence/absence of
    Type: Application
    Filed: July 26, 2017
    Publication date: June 13, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazuya SATO, Hiromasa HASHIMOTO, Tsuyoshi NISHIZAWA, Hirotaka HORIE
  • Patent number: 10319587
    Abstract: A method of manufacturing an epitaxial wafer having an epitaxial layer on a silicon-based substrate, the method of manufacturing the epitaxial wafer including epitaxially growing a semiconductor layer on the silicon-based substrate after applying terrace processing to an outer peripheral portion of the silicon-based substrate. As a result, the method of manufacturing the epitaxial wafer having the epitaxial layer on the silicon-based substrate in which an epitaxial wafer which is completely free from cracks can be obtained, is provided.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: June 11, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori Hagimoto, Masaru Shinomiya, Keitaro Tsuchiya, Hirokazu Goto, Ken Sato, Hiroshi Shikauchi, Shoichi Kobayashi, Hirotaka Kurimoto