Patents Assigned to Shin-Etsu Handotai Co., Ltd.
  • Publication number: 20240136466
    Abstract: The present invention is a method for manufacturing an epitaxial wafer for an ultraviolet ray emission device, the method including steps of: preparing a supporting substrate having at least one surface composed of gallium nitride; forming a bonding layer on the surface composed of the gallium nitride of the supporting substrate; forming a laminated substrate having a seed crystal layer by laminating a seed crystal composed of an AlxGa1-xN (0.5<x?1.0) single crystal to the bonding layer; and epitaxially growing an ultraviolet emission device layer on the seed crystal layer of the laminated substrate, the ultraviolet emission device layer having at least: a first conductive clad layer composed of AlyGa1-yN (0.5<y?1.0); an AlGaN-based active layer; and a second conductive clad layer composed of AlzGa1-zN (0.5<z?1.0). This provides a method for manufacturing an inexpensive, high-quality epitaxial wafer for an ultraviolet ray emission device.
    Type: Application
    Filed: February 16, 2022
    Publication date: April 25, 2024
    Applicants: SHIN-ETSU HANDOTAI CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Keitaro TSUCHIYA, Masato YAMADA
  • Patent number: 11965730
    Abstract: A method includes: determining height Z1 of a focus by an optical microscope having autofocus function which uses irradiation light of wavelength ?0 to adjust the focus; determining a wavelength ?1 of irradiation light used for obtaining observation image of second thin film; obtaining observation image of second thin film by using irradiation light of the wavelength ?1, while altering heights of the focus with the Z1 as reference point; calculating standard deviation of reflected-light intensity distribution within the observation image, obtaining height Z2 of the focus corresponding to a peak position where standard deviation is greatest, and calculating a difference ?Z between Z1 and Z2; correcting the autofocus function with ?Z as a correction value; and using the corrected autofocus function to adjust the focus, obtaining the observation image of the second thin film, and calculating the film thickness distribution from the reflected-light intensity distribution within the observation image.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: April 23, 2024
    Assignees: SHIN-ETSU HANDOTAI CO., LTD., UNITY SEMICONDUCTOR
    Inventors: Susumu Kuwabara, Kevin Quinquinet, Philippe Gastaldo
  • Publication number: 20240125006
    Abstract: A method for detecting a surface state of a raw material melt in a crucible in single crystal production by a CZ method in which a single crystal is pulled from the raw material melt in the crucible including: photographing a predetermined same test region of the surface of the raw material melt in the crucible simultaneously in different directions with two CCD cameras to obtain measurement images; and automatically detecting, using parallax data of the measurement images from the two CCD cameras, one or more of the following: solidification timing when a state in which the raw material is completely melted becomes a state in which solidification is formed on the surface of the raw material melt; and melting complication timing when a state in which the raw material melt has solidification on the surface of the raw material melt becomes a completely melted state.
    Type: Application
    Filed: January 26, 2022
    Publication date: April 18, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Katsuyuki KITAGAWA
  • Publication number: 20240128130
    Abstract: An evaluation method including steps of: acquiring profile measurement data on an entire surface in a thickness direction of a mirror-polished wafer; identifying a slice-cutting direction by performing first-order or second-order differentiation on diameter-direction profile measurement data on the wafer to acquire differential profiles at predetermined rotation angles and pitches, and comparing the acquired differential profiles; acquiring x-y grid data by performing first-order or second-order differentiation on profile measurement data at a predetermined pitch in a y-direction at a predetermined interval in an x-direction perpendicular to the y-direction, which is the identified slice-cutting direction; acquiring, from the x-y grid data, a maximum derivative value in an intermediate region including the wafer center in the y-direction and a maximum derivative value in upper-end-side and lower-end-side regions located outside the intermediate region; and judging failure incidence possibility in a device fab
    Type: Application
    Filed: September 14, 2020
    Publication date: April 18, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Junya SUZUKI, Masakazu SATO
  • Patent number: 11959191
    Abstract: A method for manufacturing a silicon single crystal wafer for a multilayer structure device including: using a silicon single crystal wafer with oxygen concentration of 12 ppma (JEITA) or higher and composing an NV region; and performing an RTA treatment in a nitrogen-containing atmosphere and a temperature of 1225° C. or higher, a mirror-polish processing treatment, and a BMD-forming heat treatment manufacturing a silicon single crystal wafer having at least a DZ layer with a thickness of 5 to 12.5 ?m and a BMD layer positioned immediately below the DZ layer and a BMD density of 1×1011/cm3 or higher from the silicon single crystal wafer surface. During device formation, the silicon wafer surface stress is absorbed immediately below a surface layer, distortion defects are absorbed by the BMD layer, device formation region strength is enhanced, and surface layer dislocation occurrence and extension is suppressed.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: April 16, 2024
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Wei Feng Qu, Shizuo Igawa
  • Patent number: 11958160
    Abstract: A method for slicing a workpiece with a wire saw which includes a wire row formed by winding a fixed abrasive grain wire having abrasive grains secured to a surface thereof around multiple grooved rollers, the method including feeding a workpiece to the wire row for slicing while allowing the fixed abrasive grain wire to reciprocatively travel in an axial direction thereof, thereby slicing the workpiece at multiple positions aligned in an axial direction of the workpiece simultaneously. The method includes: supplying a coolant for workpiece slicing onto the wire row when the workpiece is sliced with the fixed abrasive grain wire; and supplying a coolant for workpiece drawing, which differs from and has a higher viscosity than the coolant for workpiece slicing, onto the wire row when the workpiece is drawn out from the wire row after the slicing of the workpiece.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 16, 2024
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Koji Kitagawa, Shiro Toyoda
  • Publication number: 20240120192
    Abstract: A method of cleaning a silicon wafer in which the silicon wafer is roughened, including: forming an oxide film on the silicon wafer by SC1 cleaning, SC2 cleaning, or ozone water cleaning; cleaning the silicon wafer on which the oxide film is formed by using any one of: a diluted aqueous solution of ammonium hydroxide having an ammonium hydroxide concentration of 0.051% by mass or less; or a diluted aqueous solution containing ammonium hydroxide and hydrogen peroxide water and having an ammonium hydroxide concentration of 0.051% by mass or less and a hydrogen peroxide concentration of 0.2% by mass or less, the hydrogen peroxide concentration being four times or less the ammonium hydroxide concentration, to roughen front and rear faces of the silicon wafer.
    Type: Application
    Filed: February 21, 2022
    Publication date: April 11, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kota FUJII, Tatsuo ABE
  • Publication number: 20240117525
    Abstract: A nitride semiconductor substrate includes: a heat-resistant support substrate having a core including nitride ceramic enclosed in an encapsulating layer; a planarization layer provided on the heat-resistant support substrate; a silicon single crystal layer having a carbon concentration of 1×1017 atoms/cm3 or higher provided on the planarization layer; a carbonized layer containing silicon carbide as a main component and having a thickness of 4 to 2000 nm provided on the silicon single crystal layer; and a nitride semiconductor layer provided on the carbonized layer. This provides a high-quality nitride semiconductor substrate (a nitride semiconductor substrate particularly suitable for GaN-based high mobility transistors (HEMT) for high-frequency switches, power amplifiers, and power switching devices); and a method for producing the same.
    Type: Application
    Filed: January 26, 2022
    Publication date: April 11, 2024
    Applicants: SHIN-ETSU HANDOTAI CO., LTD., SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Keitaro TSUCHIYA, Weifeng QU, Yoshihiro KUBOTA, Kazutoshi NAGATA
  • Patent number: 11928178
    Abstract: A wafer is prepared, and a thickness shape of the prepared wafer at each position in a radial direction is measured for each of a predetermined number of angles into which 360 degrees of a circumference around the center of the wafer are divided. The thickness shape obtained by a measuring machine for each angle is approximated with a sixth or higher order polynomial, and a function of the wafer thickness at the position in the radial direction is created. The thickness shape outputted by the measuring machine and a thickness shape outputted by the function are compared with each other, and an error on the entire surface of the wafer is confirmed to be not greater than a predetermined error. After the confirmation, information of the function for each angle is attached to the wafer as data representing the wafer shape and supplied to a user.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 12, 2024
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Masato Ohnishi
  • Publication number: 20240079412
    Abstract: A nitride semiconductor substrate, including a Ga-containing nitride semiconductor thin film formed on a substrate for film-forming in which a single crystal silicon layer is formed above a supporting substrate via an insulative layer, wherein the nitride semiconductor substrate has a region where the Ga-containing nitride semiconductor thin film is not formed inward from an edge of the single crystal silicon layer being a growth surface of the nitride semiconductor thin film. This provides: a nitride semiconductor substrate with inhibited generation of a reaction mark; and a manufacturing method therefor.
    Type: Application
    Filed: January 17, 2022
    Publication date: March 7, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ippei KUBONO, Keitaro TSUCHIYA, Kazunori HAGIMOTO, Masaru SHINOMIYA
  • Publication number: 20240076800
    Abstract: A single crystal pulling apparatus includes: a pulling furnace having a central axis; and magnetic field generating apparatus around the pulling furnace and having coils, for applying a horizontal magnetic field to molten semiconductor raw material to suppress convection in crucible, in which, main coils and sub-coils are provided, as the main coils, two pairs of coils arranged facing each other are provided, two coil axes thereof are included in the same horizontal plane, a center angle ? between the two coil axes sandwiching the X-axis, which is a magnetic force line direction on the central axis in the horizontal plane, is 100 degrees or more and 120 degrees or less, as the sub-coils, a pair of superconducting coils arranged to face each other is provided and its one coil axis is aligned with the X-axis, and current values of the main coils and the sub-coils can be set independently.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 7, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroyuki KAMADA, Kiyotaka TAKANO
  • Publication number: 20240063027
    Abstract: The present invention is a method for producing an epitaxial wafer forming a single crystal silicon layer on a single crystal silicon wafer, comprising, a step of removing native oxide film on surface of the single crystal silicon wafer with hydrofluoric acid, a step of forming an oxygen atomic layer on the surface of the single crystal silicon wafer from which the native oxide film has been removed, a step of epitaxially growing the single crystal silicon layer on the surface of the single crystal silicon wafer on which the oxygen atomic layer is formed, wherein the plane concentration of oxygen in the oxygen atomic layer is 1×1015 atoms/cm2 or less. As a result, a method for producing an epitaxial wafer, that an oxygen atomic layer can be stably and simply introduced into an epitaxial layer, and having a good-quality single crystal silicon epitaxial layer is provided.
    Type: Application
    Filed: December 6, 2021
    Publication date: February 22, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Katsuyoshi SUZUKI
  • Patent number: 11898078
    Abstract: A semiconductor phosphor configured to exhibit photoluminescence upon irradiation with excitation light, including: at least one active layer made of a compound semiconductor and containing an n-type or p-type dopant; and at least two barrier layers made of a compound semiconductor and having a larger band gap than the active layer. The active layer and the barrier layers are alternately stacked. This provides a semiconductor phosphor which allows easy wavelength adjustment, high efficiency and stability.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 13, 2024
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Susumu Higuchi, Kenji Sakai, Masato Yamada, Masanobu Takahashi, Junya Ishizaki
  • Publication number: 20240026565
    Abstract: A method for measuring distance between lower end surface of heat shielding member and surface of raw material melt, the method including providing the member being located above the melt, when a silicon single crystal is pulled by the Czochralski method while a magnetic field is applied to the melt in a crucible, the method including: forming a through-hole in the member; measuring distance between the member and the melt surface, and observing position of mirror image of the through-hole with fixed point observation apparatus, the mirror image being reflected on the melt surface; then measuring a moving distance of the mirror image, and calculating distance between the member and the melt surface from a measured value and the moving distance of the mirror image, during the pulling of the crystal. The distance between the member and the melt can be precisely measured by the method.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 25, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kosei SUGAWARA, Takaki IMAI, Masahiro AKIBA, Katsuyuki KITAGAWA
  • Patent number: 11878385
    Abstract: A method for slicing an ingot with a wire saw, comprising: forming a wire row by a wire spirally wound between a plurality of wire guides and configured to travel in an axial direction of the wire; feeding an ingot held with a workpiece-feeding mechanism to the wire row for slicing; and slicing the ingot into a plurality of wafers, while supplying a slurry to a contact portion between the ingot and the wire, wherein a warp direction in a wire travelling direction of a wafer obtained in previous ingot slicing is checked in advance, and the ingot is then sliced under a condition that a warp direction in a workpiece feeding direction of a wafer to be obtained matches the checked warp direction in the wire travelling direction, so that the wafers have identical warp directions in the workpiece feeding direction and in the wire travelling direction.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 23, 2024
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Keiichi Kanbayashi
  • Patent number: 11878329
    Abstract: A method for cleaning a silicon wafer includes the steps of: supplying hydrofluoric acid onto a surface of the silicon wafer to treat the silicon wafer while rotating at a first rotational rate, stopping the supply of the hydrofluoric acid and shaking off hydrofluoric acid on the surface of the silicon wafer without supplying pure water onto the surface of the silicon wafer while rotating the silicon wafer at a second rotational rate which is the same as or faster than the first rotational rate, and supplying ozone water onto the surface of the silicon wafer to treat the silicon wafer after shaking the hydrofluoric acid off the surface while rotating at a third rotational rate which is faster than the second rotational rate. This method for cleaning a silicon wafer is capable of suppressing adhesion of water marks and particles and enhancing the wafer quality.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 23, 2024
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kensaku Igarashi, Tatsuo Abe
  • Publication number: 20240009799
    Abstract: The present invention is a polishing pad having a polishing layer for polishing surface of a wafer and a double-sided tape for attaching the polishing layer to an upper turn table of a double-side polishing apparatus, wherein, the double-sided tape has a 90° peeling adhesive strength A of 2000 g/cm or more, and a ratio A/B of the 90° peeling adhesive strength A to a 180° peeling adhesive strength B of 1.05 or more, the double-sided tape has a base material, a polishing-layer-side adhesive layer to be attached to the polishing layer, and an upper-turn-table-side adhesive layer to be attached to the upper turn table, and total thickness of the polishing-layer-side adhesive layer and the upper-turn-table-side adhesive layer is 80 ?m or less. This provides a polishing pad capable of suppressing deterioration of flatness of the wafer when performing double-side polishing of the wafer.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 11, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Junichi UENO
  • Publication number: 20240011919
    Abstract: The present invention is an inspection apparatus for inspecting a container including a light-transmittable transparent portion and configured to house a wafer, the apparatus including: a flat lamp provided to irradiate a portion to be inspected including at least a part of the transparent portion of the container with light; and a camera provided to face the flat lamp across the portion to be inspected of the container and configured to image the portion to be inspected so as to detect a foreign matter and/or a defect in the portion to be inspected of the container. This can provide an inspection apparatus and inspection method that can inspect whether a foreign matter or a defect is present inside a wafer container more certainly than visual inspection by a person.
    Type: Application
    Filed: October 6, 2021
    Publication date: January 11, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yoichi KARAKI, Shinnosuke ICHIKAWA
  • Publication number: 20240003046
    Abstract: A single crystal manufacturing including: main chamber; pulling chamber; thermal shield member provided so as to face a silicon melt; rectifying cylinder provided on the thermal shield member so as to enclose the silicon single crystal being pulled up; cooling cylinder provided so as to encircle the silicon single crystal being pulled up and including an extending portion extending toward the silicon melt; and cooling auxiliary cylinder fitted to inside of the cooling cylinder. The extending portion of the cooling cylinder includes a bottom surface facing the silicon melt. The cooling auxiliary cylinder includes at least a first portion surrounding the bottom surface of the cooling cylinder and a second portion surrounding an upper end portion of the rectifying cylinder. This enables provision of the apparatus capable of manufacturing a single crystal with a carbon concentration lower than that according to the conventional technologies.
    Type: Application
    Filed: November 1, 2021
    Publication date: January 4, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Keisuke MIHARA, Kazuya YANASE, Nobuaki MITAMURA, Kiyotaka TAKANO
  • Patent number: 11862456
    Abstract: A method for cleaning a semiconductor wafer to clean a semiconductor wafer after polishing, including: performing a first ozone-water treatment step of cleaning the polished semiconductor wafer with ozone water to form an oxide film; performing a brush cleaning step of brush-cleaning the semiconductor wafer with carbonated water after the first ozone-water treatment step; and then performing a second ozone-water treatment step including cleaning the semiconductor wafer with hydrofluoric acid to remove the oxide film, followed by cleaning with ozone water to form an oxide film again. This second ozone-water treatment step is performed one or more times.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: January 2, 2024
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kensaku Igarashi