Abstract: An electronic device has a primary coil 10; a secondary coil 20 disposed to face the primary coil 10; a coil sealing part 50 sealing the primary coil 10 and the secondary coil 20 and being made of sealing resin; a primary-side electronic element 110 electrically connected to the primary coil 10; and a secondary-side electronic element 210 electrically connected to the secondary coil 20. The primary-side electronic element 110 is provided on a primary-side extension part 60 extending from the primary coil 10 to an outside of the coil sealing part 50, or the secondary-side electronic element 210 is provided on a secondary-side extension part 70 extending from the secondary coil 20 to an outside of the coil sealing part 50.

Abstract: A semiconductor device includes: a semiconductor base body including: a p-type substrate; and an n-type first semiconductor layer; a first electrode; a second electrode; an isolation film; an insulation film; and a third electrode disposed over the insulation film. The first electrode is electrically connected to a first circuit C1 that is connected to a first power source Vin. The second electrode is electrically connected to a second circuit C2 that is connected to a second power source Vcc. The semiconductor base body further includes a p-type back gate region that is formed in at least a region of the semiconductor base body that faces the third electrode by way of the insulation film with a depth that allows the back gate region to reach the substrate. A dopant concentration of the back gate region falls within a range of 1×1010 cm?3 to 1×1015 cm?3.

Abstract: [Problem] To provide a semiconductor device capable of suppressing a channel current without increasing manufacturing processes, and capable of accurately forming a channel current suppression structure. [Solution] A semiconductor device 1 according to the present invention includes: a substrate 10; an epitaxial layer 20 formed on the substrate 10; and an insulating film 35 provided on one surface 20a side of the epitaxial layer 20. An active portion 40 provided with a predetermined element and a channel current suppression portion 50 being at a termination portion 70 side and provided outside the active portion 40 are provided on the one surface 20a side of the epitaxial layer 20 via the insulating layer 35. The channel current suppression portion 50 is provided with a trench 51 for suppressing the channel current flowing from the active portion 40 to the termination portion 70.

Abstract: A magnetic component has a primary coil 10; a secondary coil 20 disposed to face the primary coil 10; a core 500 which passes through the primary coil 10 and the secondary coil 20; and a coil sealing part 50 which seals at least the primary coil 10 and the secondary coil 20, and a part or whole of region between the primary coil 10 and the secondary coil 20 and the core 500.

Abstract: An electronic device has a primary coil 10; a secondary coil 20 disposed to face the primary coil 10; a coil sealing part 50 sealing the primary coil 10 and the secondary coil 20 and being made of sealing resin; a primary-side sealing part 150 sealing a primary-side electronic element 110 electrically connected to the primary coil 10; and a secondary-side sealing part 250 sealing a secondary-side electronic element 210 electrically connected to the secondary coil 20.

Abstract: A semiconductor apparatus according to the present invention is a semiconductor apparatus on which a plurality of external terminals are disposed. The semiconductor apparatus includes: a first lead portions having die pads, first outer leads and first inner leads; chips; second lead portions having second outer leads and second inner lead; and a resin. On at least one of the first inner leads, the second inner leads and the die pads, a terminal temperature equalizing structure which restricts a heat transfer amount of heat transferred from the chips to predetermined external terminals, and equalizes respective terminal temperatures of a plurality of external terminals is formed. According to the semiconductor apparatus of the present invention, it is possible to prevent specific external terminals from becoming extremely high temperature when the semiconductor apparatus is mounted.

Abstract: Provided is a semiconductor device in which a snubber-circuit is incorporated and can realize downsizing of a power conversion circuit into which the semiconductor device is assembled, and is flexibly applicable to various electric equipment. A semiconductor device includes a semiconductor substrate, a source electrode, a drain electrode, a plurality of trenches, a plurality of first electrodes disposed in a plurality of trenches by way of gate insulation films formed on side walls of the plurality of respective trenches, a plurality of second electrodes disposed above the plurality of first electrodes in a state where the second electrodes are spaced apart from the first electrodes, a plurality of first insulation regions, and a plurality of second insulation regions. The trenches, the first electrodes and the second electrodes are formed in stripes as viewed in a plan view. At least one of the plurality of second electrodes is connected to the drain electrode.

Abstract: An electronic device has a primary coil 10; a secondary coil 20 disposed to face the primary coil 10; a primary-side electronic element 110 electrically connected to the primary coil 10; and a secondary-side electronic element 210 electrically connected to the secondary coil 20. The primary coil 10 has a primary-side first coil 10a that is provided on another side of the secondary coil 20, and a primary-side second coil 10b that is provided on one side of the primary-side first coil 10a. A connecting part 19 connecting the primary-side first coil 10a and the primary-side second coil 10b is provided and passes through a space of the secondary coil 20.

Abstract: A semiconductor device according to the present invention includes: a circuit board; a semiconductor element having a main electrode; a metal frame; and a metal plate having a flat plate shape, the metal plate being disposed between the metal frame and the main electrode, wherein the metal plate and a conductive bonding material, form a stress relaxation structure which relaxes a stress applied to metal plate and the conductive bonding material, disposed between the metal frame and the semiconductor element, and the stress relaxation structure is configured such that a thickness of the metal plate is smaller than a thickness of the metal frame, and at least one convex portion is formed on the metal plate at a position which corresponds to the main electrode. The semiconductor device according to the present invention can relax a stress applied to a conductive bonding material between a semiconductor element and a metal frame even when a relatively thick metal frame is used.

Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.

Abstract: An electronic device includes: a substrate at which an electronic component is mounted; and a resin case configured to accommodate the substrate internally, in which: the case has an attachment portion configured to attach the case to a flat plate-shaped fixing portion of a fixture target by the fixing portion being inserted into the attachment portion and the attachment portion engaging with the fixing portion; the attachment portion has a first pressing portion having a convex portion that is inserted into a concave portion of the inserted fixing portion, and a pair of second pressing portions that hold between them respective side faces of the inserted fixing portion; and leading end sides of the pair of second pressing portions abut on the inserted fixing portion and are resiliently deformed in directions away from each other, holding between them the respective side faces of the fixing portion in a state in which the leading end sides have been resiliently deformed.

Abstract: A semiconductor device includes: an inner substrate on which a semiconductor chip is mounted, and has a surface on which terminals including electric path terminals are formed; a lead frame which has a chip connecting electrode portion which is electrically connected to a surface of the semiconductor chip via a conductive bonding member, substrate connecting electrode portions which are electrically connected to the electric path terminals of the inner substrate, and horizontal surface support portions which bulge to the outside from the chip connecting electrode portion or the substrate connecting electrode portions; and pin terminals which are mounted upright over the inner substrate in a direction perpendicular to flat surfaces of the substrate connecting electrode portions of the lead frame, wherein the horizontal surface support portions bulge to the outside of the inner substrate.

Abstract: An electronic module has a first substrate 11; a first electronic element 13 provided on one side of the first substrate 11; a first connection body 60 provided on the one side of the first electronic element 13; a second electronic element 23 provided on the one side of the first connection body 60; and a second connection body 70 provided on the one side of the second electronic element 23. The first electronic element 13 and the second electronic element 23 do not overlap in a plane direction.

Abstract: A wide gap semiconductor device has a wide gap semiconductor layer 10; and a metal electrode 20 disposed on the wide gap semiconductor layer 10. The metal electrode 20 has a monocrystalline layer 21 having a hexagonal close-packed (HCP) structure in an interface region between the metal electrode 20 and the wide gap semiconductor layer 10. The monocrystalline layer 21 has a specific element-containing region 22 containing O, S, P or Se.