Patents Assigned to Sidense Corp.
  • Publication number: 20100002527
    Abstract: A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device.
    Type: Application
    Filed: December 20, 2007
    Publication date: January 7, 2010
    Applicant: SIDENSE CORP.
    Inventor: Wlodek Kurjanowicz
  • Publication number: 20090290434
    Abstract: A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.
    Type: Application
    Filed: December 20, 2007
    Publication date: November 26, 2009
    Applicant: SIDENSE CORP.
    Inventor: Wlodek Kurjanowicz
  • Publication number: 20090262566
    Abstract: A memory array having both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. All memory cells of the memory array are configured as one-time programmable memory cells. Any number of these one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming. Manufacturing of such a hybrid memory array is simplified because both types of memory cells are constructed of the same materials, therefore only one common set of manufacturing process steps is required. Inadvertent user programming of the mask programmable memory cells is inhibited by a programming lock circuit.
    Type: Application
    Filed: December 20, 2007
    Publication date: October 22, 2009
    Applicant: SIDENSE CORP.
    Inventor: Wlodek Kurjanowicz
  • Publication number: 20090251943
    Abstract: Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate properly. The OTP testing system includes one or both of column test circuitry and row test circuitry. The column test circuitry charges all the bitlines to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a test wordline. The bitline voltages can be sensed, thereby allowing for testing of the column decoding and sense amplifier circuits. The row test circuitry charges a test bitline to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a wordline of the OTP memory array. This test bitline voltage can be sensed, thereby allowing for testing of the row decoding and driver circuits.
    Type: Application
    Filed: December 23, 2008
    Publication date: October 8, 2009
    Applicant: SIDENSE CORP.
    Inventor: Wlodek KURJANOWICZ
  • Publication number: 20090250726
    Abstract: A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits.
    Type: Application
    Filed: November 7, 2008
    Publication date: October 8, 2009
    Applicant: Sidense Corp.
    Inventor: Wlodek KURJANOWICZ
  • Publication number: 20090180307
    Abstract: A program lock circuit for inhibiting programming of memory cells. A memory array can have both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. Since the one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming, these mask programmed cells are still electrically programmable, thereby destroying the originally stored data. The programming lock circuit inhibits programming of the mask programmed cells by detecting an activated wordline during a programming operation, and then immediately disabling or decoupling the high voltage supply that is provided to the wordline drivers. Mask programmed transistor elements coupled to each wordline detect the wordline voltage and disable the high voltage supply. A mask programmable master lock device can be provided to inhibit all the rows in the memory array from being programmed.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 16, 2009
    Applicant: SIDENSE CORP.
    Inventor: Wlodek Kurjanowicz
  • Publication number: 20090154217
    Abstract: A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
    Type: Application
    Filed: February 20, 2009
    Publication date: June 18, 2009
    Applicant: SIDENSE CORP.
    Inventors: Wlodek KURJANOWICZ, Steven SMITH
  • Patent number: 7511982
    Abstract: A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 31, 2009
    Assignee: Sidense Corp.
    Inventors: Wlodek Kurjanowicz, Steven Smith
  • Publication number: 20080246098
    Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.
    Type: Application
    Filed: June 16, 2008
    Publication date: October 9, 2008
    Applicant: SIDENSE CORP.
    Inventor: Wlodek KURJANOWICZ
  • Patent number: 7402855
    Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: July 22, 2008
    Assignee: Sidense Corp.
    Inventor: Wlodek Kurjanowicz