Abstract: A computing system implementing a design verification system can elaborate a mixed-signal circuit design having a complex sandwich hierarchy using a standard digital solver and a standard analog solver, as opposed to a tightly coupled custom elaboration engine. The design verification system can parse the mixed-signal circuit design to identify analog design blocks and flatten the analog design blocks into the structural proxy blocks having parameter connections to digital design blocks in the mixed-signal circuit design. The design verification system can replace an analog portion of the mixed-signal circuit design with the structural proxy blocks and elaborate the structural proxy blocks and digital design blocks associated with a digital portion of the mixed-signal circuit design. The design verification system can elaborate the analog portion of the mixed-signal design and simulate the elaborated analog portion with an analog simulator and the elaborated digital portion with a digital simulator.

Abstract: A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; a test response compactor configured to compact the test responses; and shuffler circuitry inserted between outputs of the scan chains and inputs of the test response compactor, the shuffler circuitry comprising state elements configured to delay output signals from some of the scan chains for one or more clock cycles based on a control signal, the control signal varying with the test patterns.

Abstract: Systems and methods for designing and manufacturing an additive manufacturing (AM) model. A method includes computing a wedge plane and initial toolpath for an AMmodel based on a breaking angle. The method includes trimming an excess toolpath of the AM model using a breaking plane. The method includes building the toolpath along the normal of a first layer and trimming based on a next layer. The method includes building a next wedge of the toolpath in the direction of a wedge plane used to trim a previous wedge The method includes storing the toolpath.

Abstract: A system may include a resource acquisition engine configured to acquire a set of computing resources for execution of an application flow comprising multiple invocations to an EDA application. The system may also include a resource provision engine configured to provide the set of computing resources for execution of a first EDA process of the EDA application launched by a first invocation in the application flow and identify a second invocation subsequent to the first invocation in the application flow, the second invocation to launch a second EDA process of the EDA application. The resource provision engine may be further configured to, without releasing the set of computing resources provided to the first EDA process, proxy the set of computing resources into a proxied set of computing resources and provide the proxied set of computing resources for execution of the second EDA process of the EDA application.

Abstract: A system and method is provided for determining grasping positions for two-handed grasps of industrial objects. The system may include a processor configured to determine a three dimensional (3D) voxel grid for a 3D model of a target object. In addition, the processor may be configured to determine at least one pair of spaced apart grasping positions on the target object at which the target object is capable of being grasped with two hands at the same time based on processing the 3D voxel grid for the target object with a neural network trained to determine grasping positions for two-handed grasps of target objects using training data. Such training data may include 3D voxel grids of a plurality of 3D models of training objects and grasping data including corresponding pairs of spaced-apart grasping positions for two-handed grasps of the training objects. Also, the processor may be configured to provide output data that specifies the determined grasping positions on the target object for two-handed grasps.

Abstract: A method, and corresponding systems and computer-readable mediums, for designing and manufacturing a part. A method includes receiving part data for a part to be manufactured. The method includes creating a set of balls and beams in a computer-aided design (CAD) model, in a patterning structure and based on the part data. The method includes constructing a steady lattice structure in the CAD model. The method includes displaying the CAD model including the steady lattice structure.

Abstract: This application discloses a computing system implementing a parasitic extraction tool to generate a parasitic model from physical design layout of an integrated circuit. The computing system also can implement a machine-learning classifier that, when trained with a training data set, can classify the physical design layout based on physical or electrical characteristics associated with the physical design layout, and can utilize the classification to select a set of scaling coefficients. The computing system can apply the selected set of the scaling coefficients to adjust coupling capacitances in the parasitic model and generate a parasitic netlist for the physical design layout. The computing system can generate the training data set by determining sets of the scaling coefficients from the test physical design layouts and labeling the test physical design layouts with the sets of the scaling coefficients.

Abstract: A method of identifying elements in a design layout having multiple levels of hierarchical cells, each cell having one or more geometric elements, may include selecting a cell from a list of candidate cells for a level of a hierarchy; applying a local rule to the selected cell; identifying each selected cell that includes a geometric element that passes the local rule; building a list of candidate cells for a next-higher level of the hierarchy according to the identified cells; repeating the selecting, identifying, and building operations for each higher level of the hierarchy; and when a highest level of the hierarchy has been processed, returning and storing the list of candidate cells as the global solution for the applied local rule.

Abstract: Systems and methods for calculating a printed area metric indicative of stochastic variations of the lithographic process are disclosed. Lithography is a process that uses light to transfer a geometric pattern from a photomask, based on a layout design, to a resist on a substrate. The lithographic process is subject to random stochastic phenomena, with the resulting stochastic randomness potentially becoming a major challenge. To characterize the stochastic phenomena, a printed area metric may be generated analytically (rather than via simulations) and comprise one or more defined moments for a printed area distribution associated with the printed area that are indicative of one or more aspects associated with printing. For example, the printed area metric may be indicative of the likelihood of printing within the printed area or the variance of printing within the printed area due to stochastic randomness in one or both of exposure or resist process.

Abstract: A computer-aided design (CAD) system may support detection of internal channel networks for 3D printing and may include a CAD model access engine and a channel network detection engine. The CAD model access engine may access a CAD model of a physical object to be constructed through 3D printing. The channel network detection engine may detect an internal channel network included in the CAD model of the physical object, including by identifying channel openings along a surface of the CAD model that satisfy an opening size threshold and recursively identifying internal faces of the CAD model that form the internal channel network, wherein the internal faces are faces of the CAD model that are internal to the surface of the CAD model. The channel network detection engine may also perform a channel verification on the identified internal channel network to support the 3D printing of the physical object.

Abstract: A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit. The computing system also can perform a parasitic extraction process on the geometric layout design by utilizing the device-level layout design for the integrated circuit. The computing system implementing the parasitic extraction process can sub-divide a conductor in the device-level layout design into multiple sub-divided conductor portions based on conversion rules corresponding to the physical properties of layers for the integrated circuit described in a technology file. The computing system can generate a physical layout design of the integrated circuit from the device-level layout design having the sub-divided conductor portions based on the technology file.

Abstract: A system may cause a display device to display a graphical representation of a geometric model of a part having a plurality of features that are individually selectable in a work space of a graphical user interface and may receive a selection input representative of a command to select one or more features of the geometric model. The system may also determine at least one displayed characteristic capable of being visually perceived by a user that the geometric model or a portion thereof has with respect to the workspace in terms of size, orientation, and/or position. Also, the system may carry out a first selection from among either a coarser selection of the features or a finer selection of the features of the geometric model based on an input location and based on the determined at least one displayed characteristic of the geometric model or portion thereof.

Abstract: A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Abstract: A system and method is provided that facilitates optimizing tool paths based on thermal/structural simulations of a part produced via a 3D-printer. A processor may carry out a first simulation of the part being additively produced according to a first set of tool paths that correspond to instructions usable to drive the 3D-printer to produce the part. The first simulation may include: determining a hexahedral mesh of the part that includes a plurality of hexahedron elements; determining an order of the elements of the mesh to deposit for additively producing the part based on the first set of tool paths; and simulating an incremental deposit of each of the elements of the mesh in the order that the elements are determined to be deposited.

Abstract: Various aspects of the disclosed technology relate to predicting physical failure analysis-oriented diagnosis resolution. Fault simulation is performed on a circuit design to derive test responses for a set of faults and test patterns for testing circuits fabricated according to the circuit design. The set of faults is grouped into groups of equivalent faults based on the test responses. A group of equivalent faults consists of faults having the same test responses for all test patterns in the test patterns that can activate the faults. A PFA (physical failure analysis)-oriented diagnosis resolution evaluation value is computed by averaging weighted sizes of the groups of equivalent faults. The weight factors for the groups of equivalent faults with sizes greater than a certain number being smaller than the weight factors for rest of the groups of equivalent faults.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A system and method is provided for visual traceability of requirements for products. The system may include a processor configured to generate a user interface through a display device that outputs a listing of at least a portion of a plurality of requirements for a product based on data stored in a data store that specifies associations between requirements and one or more of a plurality of components included in the product. The processor may receive a first input through at least one input device that is representative of a first selection of at least one of the plurality of requirements.

Abstract: A computing system implementing an optical proximity correction model verification tool can determine parameters for design patterns associated with an integrated circuit described in a layer file, and determine differences between the design patterns and calibration patterns utilized to calibrate an optical proximity correction (OPC) model configured to predict a printed image on a substrate corresponding to a layout design for the integrated circuit by determining distances between the determined parameters for the design patterns and parameters for the calibration patterns. The computing system can classify the design patterns with a modeling capability of the OPC model for the design patterns based on the differences between design patterns and the calibration patterns and possibly error rates of the OPC model associated with the calibration patterns or lithographic difficulty of the calibration patterns. The computing system can modify the layer file to include the classifications of the design patterns.

Abstract: Systems and methods for validation of photonics device layout designs. A method includes receiving, by a computer system, a rule deck and a layout design. The layout design includes silicon photonics (SiP) structures. The method includes performing a verification process to produce verification results. The verification results include violations and the violations include SiP violations. The method includes performing SiP spacing filtering to filter the SiP violations into true SiP violations and false SiP violations. The method includes storing the true SiP violations in a result database.

Abstract: A method of reconfiguring an addressing mechanism in a system-on-chip comprising system circuitry and monitoring circuitry having tree-structured units for routing communications through the system, includes sending a discovery message, receiving discovery responses from the units, each discovery response identifying the number of individually addressable entities in that unit and those units in the branch above that unit; in response to not receiving a response from one or more units, determining that one of those units is defective; enabling a crosslink between a first unit in the same branch as the defective unit and a second unit in an adjacent branch; sending a further discovery message; receiving a further discovery response from the second unit identifying the number of individually addressable entities in that second unit, those units in the branch above that second unit, the first unit, and those units in the branch above the first unit; and reconfiguring the address of the crosslink so as to cause a