Abstract: Systems and methods of motion compensated frame rate conversion are described herein. These systems and methods convert an input video sequence at a first frame rate to an output video sequence at a second frame rate through a novel motion estimation and motion vector processing stage that produces a motion field having a plurality of motion vectors that describe the movement of objects between input video frames from the perspective of an interpolated video frame. A subsequent motion compensated interpolation stage then constructs the interpolated video frame using an adaptively blended combination of a motion compensated prediction and a temporal average prediction of the pixel values from the input video frames.

Abstract: A system and method utilize a dual correlation, one for the synchronization pattern (sync correlation) and one for the channel equalization pattern (CE correlation), to determine where the channel equalization pattern starts and thus establish frame synchronization. The system and method compare the two correlations and decides on the start of the channel equalization symbols when the CE correlation is larger than the sync correlation.

Abstract: The present invention provides a framework for the processing of blocks between two data frames and in particular application to motion estimation calculations in which a balance among the performance of a motion search algorithm, the size of on-chip memory to store the reference data, and the required data transfer bandwidth between on-chip and external memory can be optimized in a scalable manner, such that the total system cost with hierarchical embedded memory structure can be optimized in a flexible manner. The scope of the present invention is not limited to digital video encoding in which motion vector is part of information to be encoded, but is applicable to any other implementation in which difference between any two data frames are to be computed.

Abstract: In embodiments of the present invention improved capabilities are described for sensing a change in a network topology using a discovery node in a mesh network; transmitting an explore frame, based at least in part on the sensed change, from the discovery node to a destination node using an intermediate node; receiving a response to the explore frame from the destination node; determining at least one functional network route from the discovery node to the destination node based at least in part on route information received in association with the response to the explore frame, wherein the route information includes a node path; and transmitting an instruction to the destination node from the discovery node based on a reverse node path.

Abstract: An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the register upon receipt of a selection signal at the guard input. A lookup table is dynamically programmed with logic to implement an upcoming branching portion of program code. Upon evaluation of the branch conditions of the branching portion of code, the lookup table outputs a selection signal for writing the correct results of the branching portion of code based on the evaluation of the branch condition statements and the truth table programmed into the lookup table to the result register.

Abstract: An ultra wideband receiver, based on multiband orthogonal frequency division multiplexing (MB-OFDM), combines digital data from multiple channels after signal processing and before decoding. The receiver provides a master controller that synthesizes packet synchronization, frame synchronization, and sampling frequency offset information from multiple channels into signals that simultaneously control all channels of the receiver.

Abstract: A computer-implemented method, executable software product, and system for performing a test of an audio/video playback device are described. The audio/video playback device includes at least one main processor, interfaces, and additional processors. The main processor(s) communicate with the additional processors through the interfaces. The method, software product, and system include monitoring at least part of the interfaces for communications between the main processor(s) and the additional processors. The method, system and software product also include storing the communications in a raw format during the test. The method, software product and system also include translating the communications from the raw format to human-readable format after the test concludes and displaying the human-readable format of the communications. In some aspects, the method and system also include reading and storing run time data during the test such that the reading and storing is Heisenberg-friendly.

Abstract: In accordance with the teachings described herein, systems and methods are provided for enhancing the image quality of video. One or more filters may be used to filter a received video signal to generate a vertical filtered output, a horizontal filtered output and a diagonal filtered output. One or more amplification components may be used to apply separate gains to each of the vertical, horizontal and diagonal filtered outputs to generate a vertical enhancement signal, a horizontal enhancement signal and a diagonal enhancement signal. One or more summation components may be used to combine the vertical, horizontal and diagonal enhancement signals with the video signal to generate an enhanced video signal.

Abstract: An ultra-wideband clear channel assessment system uses a double-window energy technique for energy detection, which indicates a clear or busy channel.

Abstract: A system and method enable the fast decoding of a front end of data (e.g., a header) that is convolutionally encoded by treating the front end as a block code. The system and method receive the convolutionally encoded data; extract a finite sized block from the data; and decode the extracted block using a block error correction decoding method. A Viterbi decoder can then be used to decode the remainder of the encoded data based on the decoded block.

Abstract: The present invention provides a method for matching the rate of presentation of digital video data at a receiver/client with the rate the server is serving the data without the need of a voltage control oscillator or other hardware. An embodiment of the invention compares the presentation time at the receiver with the server elapsed time estimated from timestamp values on the served data. When the presentation time and the server elapsed time differ by an unacceptably large amount, an adjustment is made to the audio data stream to re-synchronize the presentation time with the elapsed time, which effectively also synchronizes the overall presentation rate with the overall server rate. The video data stream is then synchronized to the adjusted audio stream. The video data stream and audio data stream are converted to analog signals for presentation.

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

Abstract: The invention enables automatic gain control in ultra wideband applications over multiple channels and frequency bands.

Abstract: A method is presented for packet detection and symbol boundary location using a two-step sign correlation procedure. When the correlation crosses a threshold, a packet detection signal is generated to initiate processing of downstream blocks, and a symbol boundary location signal is generated for use in aligning data during processing.

Abstract: The present invention increases the difficulty of reverse engineering sensitive information protected by an encryption algorithm by increasing the difficulty associated with tracing the code that generates the key or the encryption algorithm. This is accomplished by generating the key, used to encrypt and decrypt the sensitive information, as a function of the program instruction values of the procedures used to generate the key and perform the decryption of the sensitive information. Thus, if the key generation code or the decryption code is modified (such as (but without limitation) by placement of a breakpoint, a trace function, or a halt instruction in the code) the resulting key will be different from the key used to encrypt the sensitive information and the decryption attempt will fail.

Abstract: A receiver sets weights for an antenna array according to a series of algorithms including an energy algorithm, a least squares algorithm and a least mean square algorithm.

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an intepolating comparator. The intepolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

Abstract: The present invention is related to a switch for use in wireless communication systems. In one embodiment, the switch can concurrently process data from multiple mobile stations and supports full duplex, i.e., allowing receiving and transmitting data at the same time. The switch can concurrently communicate with other switches and/or mobile stations in the basic service set (BSS) of that switch. A switch may be considered an access point commonly used in other approaches. However, systems using the switch do not need to use an Ethernet switch commonly found in WLAN communication systems that use access points. Switches may be set up in a master-slave scheme wherein a master switch communicates with its slave switches, and slave switches communicate with one another through the master switch. If the data is for a mobile station in the same BSS of the switch, then, via a switch controller, the switch passes the data from the receiving path to the transmitting path.

Abstract: The invention enables automatic gain control in ultra wideband applications over multiple channels and frequency bands.

Abstract: A device that converts non-visible electromagnetic energy into light. The device includes a cylindrical electromagnetic resonator with a central through hole, a dielectric (preferably ceramic) material surrounded by symmetrically displaced through holes surrounding the central through hole. The device also includes a base and probes connected to the base. The probes are placed to introduce non-visible electromagnetic energy into the resonator. The device also includes a plasma lamp placed in the central through hole. The plasma lamp is placed to convert the non-visible electromagnetic energy into light. Preferably, the resonator is composed of a ceramic with a metalized surface except for inside the through holes.