Abstract: A bipolar input circuit for regulating the current/voltage level at the base of a switching transistor (QA) provides a capacitively-controlled discharge path from the base through a discharge transistor (QC) when an input signal (V.sub.I) makes certain voltage transitions. The base of the switching transistor responds to the voltage at an emitter (E1) of an input transistor (QB) which has another emitter (E2) coupled to the base of the discharge transistor. Its base is further coupled to a capacitor (C) which controls the discharge path.

Abstract: In an improved method for growing an oxide layer on a silicon surface of a semiconductor body, the semiconductor body is first provided with a silicon surface. A first oxide layer portion is then grown over the silicon surface in a first thermal oxidation process at a temperature of less than about 1000.degree. C. The semiconductor device is then annealed in a nonoxidizing ambient at a temperature above about 1000.degree. C., and finally a second oxide layer portion is then grown over the first oxide layer portion in a second thermal oxidation process to complete the growth of the oxide layer. The silicon surface may be of either polycrystalline or monocrystalline material. This method avoids both the dopant outdiffusion problems associated with present high-temperature oxidation processes and the stress-related irregularities associated with known low-temperature oxidation processes.

Abstract: A sense amplifier with two input control stages whose input voltages are equalized during a precharge cycle by a switching means.

Abstract: A phase detector for use with a phase locked loop where the input has missing pulses. The detector processes two input frequencies and generates either a pump-up or a pump-down signal on separate outputs. The reference input may have missing transitions, as often happens in recovering the clock from encoded data. The phase detector comprises three bistable flip-flops and a gate interconnected to respond to the two input frequencies to produce either a pump-up pulse of variable width proportional to the phase difference between the pulses of the two input frequencies or a fixed width pump-down pulse.

Abstract: A bipolar signal translator contains a pair of transistors (Q1 and Q2) arranged as a current mirror with their emitters coupled to a voltage supply (V.sub.EE) by way of a pair of impedance elements (R4 and R5) that improve stability. Their collectors are coupled through another pair of impedance elements (R1 and R2) to an input transistor (Q4 or Q5) and to a device circuit (D1 and D2, D3 and D4, or Q4). The collector of one of the current-mirror transistors (Q2) is coupled to the base of an output transistor (Q3) whose collector is preferably coupled through an output impedance element (R3) to a current-control transistor (Q6) that improves power utilization.

Abstract: A novel write circuit arrangement for an EEPROM type memory system operable in response to the difference between the information stored in each addressed cell and the information to the be stored therein during a writing cycle and writing information into only those addressed cells for which a difference exists regardless of whether the difference indicates to charge or discharge the cell. The arrangement also can simultaneously charge one cell of a byte while discharging another cell of the same byte.

Abstract: A device for testing continuity and current leakage at leads of an electronic circuit such as an integrated circuit has a contact structure (16) having test terminals (T1-T28) for contacting the leads. A first and a second of the leads are power supply leads respectively contactable with a first and a second of the test terminals (T14 and T28 or T26). Continuity/leakage detection is done with one or more corresponding detection circuits (D1-D28). Each detection circuit has a channel along which both continuity and leakage are tested. A supply switching circuit (26) appropriately switches voltages between values suitable for continuity testing and values suitable for leakage testing.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The minor portion has a lower net impurity concentration than the major portion and extends to a considerably lesser depth. An impurity is introduced into the major and minor portions to form a second region (24) of first type conductivity. An impurity is introduced into the second region to form a third region (30) of second type conductivity spaced laterally apart from the minor portion. Metallization is then performed to create at least one Schottky rectifying contact (32) with the major portion and ohmic contacts (38, 36, and 34) with the substrate and second and third regions.

Abstract: Electromigration resistance of aluminum alloy conductors in semiconductor devices is found to significantly increase by rapidly annealing the conductors by employing an annealing cycle with a peak temperature of 520.degree.-580.degree. C. and a cycle time of about 5 to 30 seconds such as is developed by high intensity CW lamps.

Abstract: A memory system of the EEPROM type in which a separate writing circuit is provided for each cell of a related byte thereby permitting one cell to be charged while the other can be simultaneously discharged.

Abstract: A multi-stage amplifier (21, 22, 23, or 24) has three or more amplifier stages (A1, A2, and A3) arranged in a capacitatively nested configuration for frequency compensation. The technique consists of nesting two of the stages together with a pole-splitting capacitor (C1) to form a stable device (21 or 22) and then nesting this device and a third of the stages together with another pole-splitting capacitor (C2) to form the amplifier.

Abstract: A differential amplifier operable between a pair of supply voltages that define a rail-to-rail supply range contains a pair of differential portions (20 and 22) that together provide representative signal amplification across the supply range, although neither differential portion individually does so. A current control (24) regulates operating currents (I.sub.N and I.sub.p) for the differential portions in such a way that the amplifier transconductance can be controlled in a desired manner as the common-mode part (V.sub.CM) of the amplifier input signal (V.sub.I+ and V.sub.I-) varies across the supply range. The transconductance is typically controlled to be largely constant. A summing circuit (26) selectively combines internal currents (I.sub.A, I.sub.B, I.sub.C, and I.sub.D) from the differential portions to generate at least one output signal (I.sub.O+ and I.sub.O-) representative of the input signal.

Abstract: A voltage reference for providing a reference voltage (V.sub.AB) between a pair of terminals (A and B) contains a diode (D) and a bipolar transistor (Q) whose base is coupled to one electrode of the diode. The collector of the transistor is coupled to a node (C) between one of the terminals (A) and the other electrode of the diode. The emitter of the transistor is coupled to the other terminal (B).

Abstract: A bipolar impedance buffer contains an input transistor (Q1) whose emitter is coupled to that of a like-polarity intermediate transistor (QN). Its collector is coupled to the base of a like-polarity output transistor (QO), while its base is coupled to the collector of an opposite-polarity transistor (QP). A resistor (RN) coupled between the base and collector of the intermediate transistor significantly reduces the output settling time.

Abstract: A differential amplifier circuit contains a pair of complementary input portions (3, 5 and 4, 6). The input portions amplify a common differential input signal to produce corresponding amplified differential signals which are supplied to a summing section that operates as a modulated current mirror to produce an output signal representative of the input signal. The summing section contains a pair of like-polarity first and second amplifiers (13 and 14) and a pair of like-polarity third and fourth amplifiers (19 and 20) complementary to the other amplifiers. A pair of impedance elements (11 and 12) are coupled between a first voltage supply (ground reference) and the third and fourth amplifiers. A pair of current sources, typically impedance elements (8 and 9), are coupled between a second voltage supply (+B) and the first and second amplifiers.

Abstract: A signal translator for converting an input voltage (V.sub.I) into an output voltage (V.sub.O) at a different level contains a primary element stack (10) and a similarly-configured image element stack (12), both coupled between the sources of a potentially first variable supply voltage (V.sub.CC) and a normally constant second supply voltage (V.sub.EE). A reference voltage (V.sub.R) is supplied to both a primary-stack transistor (Q2) which provides the output voltage and an image-stack transistor (Q4) which provides a feedback signal (V.sub.F). A feedback circuit (14) formed with an amplifier (16) and a shifting circuit (18) response to the feedback signal to supply the reference voltage at such a value as to compensate the output voltage for changes in the first supply relative to the second supply voltage is particularly useful for CTL-to-TTL logic.

Abstract: A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The variable-threshold FET has its source coupled to the drain of one of the cross-coupled FET's, its insulated-gate electrode coupled to the drain of the other of the cross-coupled FET's, and its drain coupled to a power supply. A pair of impedance elements (R1 and R2) are coupled between the drains of the cross-coupled FET's, respectively, on one hand and the power supply on the other hand. Just before a power shutdown which causes the data bit to evaporate, the power supply is pulsed to a suitable level to cause the bit to be transferred to the non-volatile location. When power is restored to the normal level, the original data bit automatically returns to the volatile location.

Abstract: A bipolar differential amplifying circuit contains a pair of input transistors (3 and 4) for receiving a differential input signal, a pair of differentially-configured first and second transistor circuits (5 and 6) coupled to the input transistors, and a subtracting circuit (11 and 12) for comparing the sum of the currents through first collectors (5C.sub.1 and 6C.sub.1) of the transistor circuits with the current through a second collector (6C.sub.2) of the second transistor circuit to generate an output signal representative of the input signal. A PN diode (13) is coupled to a second collector (5C.sub.2) of the first transistor circuit. The voltages at the collectors are very close, thereby yielding a high common-mode rejection ratio for the input signal.