Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.

Abstract: An amplifier circuit for sensing and refreshing stored information, utilized with a voltage supply. The amplifier is of the type that is capable of assuming first and second conditions in response to signals at first and second input nodes. The circuit comprises first and second cross coupled devices each capable of assuming a high and low conduction state. Restore circuitry means is provided connected between the active devices and the voltage supply for selectively connecting the supply solely to the device assuming a low conduction state. In a dynamic random access memory embodiment means is further provided for alternately precharging the nodes to a predetermined state and applying stored information to the nodes to cause the amplifier to assume first and second conditions in response to stored information.

Abstract: A TTL circuit having a pair of current sources (R2/V.sub.CC and R2/V.sub.CC) and a pair of transistors (Q1 and Q2) arranged in a standard TTL input/inverting configuration has hysteresis at the input signal (V.sub.X) for providing noise protection. A hysteresis circuit (10) suitably containing another current source (R3/V.sub.CC) coupled to the base of the inverting transistor (Q2) and a rectifier (12) coupled between the collector of the inverting transistor and the current source (R1/V.sub.CC) coupled to the base of the input transistor (Q1) provides the hysteresis at the circuit switching points.

Abstract: A layer of a conductive material consisting of aluminum alone or in combination with a small percentage of copper and/or silicon is formed on a semiconductor surface in a two-step deposition process in such a manner as to largely avoid serious continuity defects in the layer.

Abstract: A film of titanitum-tungsten nitride is used to provide the dual function of a fuse link between a semiconductive device and an interconnect line in a memory array and of a barrier metal between another metal and a semiconductor region.

Abstract: A bipolar voltage translator contains a pair of differentially coupled transistors (Q1 and Q2) for converting an input voltage (V.sub.IN) supplied to one (Q1) of the pair into an output voltage (V.sub.OUT) taken between the other (Q2) and a first resistor (R9). A further transistor (Q4) coupled through a second resistor (R12) to a V.sub.EE supply provides current for the differential pair. A voltage reference circuit (10) containing at least three serially coupled diodes (S5, J3, and J4) with a resistive voltage divider (R13 and R14) across an intermediate one (J3) of the diodes provides the current-source transistor with a reference voltage (V.sub.REF2) that equals V.sub.EE +(1+.alpha.)V.sub.BE where .alpha. is 0.2-3.0. The ratio of the first resistor to the second is desirably .beta./.alpha. where .beta.is the output voltage swing divided by V.sub.BE. If .beta. is 1 and the transistors are NPN devices, the output voltage level is suitable for current tree logic.

Abstract: A MOS power-on reset circuit includes Schmitt trigger circuit and an inverter. The Schmitt trigger circuit comprises first, second, and third depletion transistors serially connected between reference potential and supply voltage. The first and second depletion transistors are connected at a first junction point, and the second and third depletion transistors are connected at a second junction point. The gates of the first and second depletion transistors are commonly connected for receiving an input substrate bias voltage. An enhancement transistor is connected between the first junction point and supply voltage. The gates of the enhancement transistor and the third depletion transistor are commonly connected to the second junction point, which is the output of the Schmitt trigger circuit and which is coupled to the inverter from which the output voltage is taken.

Abstract: A read resettable memory circuit contains a flip-flop circuit (10) consisting of a flip-flop (FF) and an edge-triggered control circuit (CC) and a fall-through latch (16). The control circuit sets the flip-flop in response to a selected edge transition in a first clock (.0..sub.1) when an appropriate external logical set signal (S) is received and resets the flip-flop in response to a selected edge transition in a second clock (.0..sub.2) when an appropriate feedback logical reset signal (R) is received. The latch provides the reset signal at a value corresponding to the current logic state of the flip-flop during each period running from the selected edge transition of the second clock to its opposite edge transition and at a value corresponding to the logic state of the flip-flop that exists just before each opposite edge transition of the second clock during each remaining following period.

Abstract: A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.

Abstract: A central processing unit capable of executing the IBM System/370 Universal Instruction Set is disclosed. The instruction set establishes the functional specifications for the processing unit, features of which include: 8-bit (byte) alphanumeric coding, 4-bit packed decimal coding (2 digits per byte), two's complement fixed-point binary arithmetic, two levels of indexing, sixteen 32-bit (4 byte) addressable general registers, four 64-bit floating point registers, and program status word and control registers. Principal features of the hardware architecture include the use of a single main data/instruction bus, transfers to and from the main bus being made under encoded microprogram control, and placement of the fixed-point binary arithmetic logic unit elements and the associated sixteen general registers on a single cascaded group of LSIC chips which operate under control of the microcode.

Abstract: A bistable switching circuit contains a pair of like-polarity input transistor circuits (Q1 and Q2) arranged in a differential configuration to receive a corresponding pair of input signals. A pair of like-polarity cross-coupled transistor load circuits (Q3 and Q4) complementary to the input transistor circuits are coupled to them. A pair of resistive elements (R1 and R2) are coupled between a voltage supply (V.sub.CC) and the load transistor circuits. An output transistor (Q5) complementary to the input transistor circuit has its control electrode and one of its flow electrodes coupled across one (Q4) of the load transistor circuits. When the input signals assume values capable of causing the output transistor to turn on, no current flows in the output transistor until regeneration occurs in the load transistor circuits -- i.e., until they switch states.

Abstract: A field-programmable logic array (FPLA) circuit of both the single level logic type containing a programmable AND/NAND gate array and the multiple level logic type containing a programmable OR/NOR gate array responsive to data from a programmable AND/NAND gate array has the programmable capability for enabling certain device pins to switch between functioning as data output pins and data input pins. A sequential logic FPLA circuit containing the basic elements of the multiple level logic device has a plurality of JK flip-flops for on-chip data storage. Selected flip-flops may be directly loaded from pins also operable for supplying output data, may be dynamically converted to function as D-type flip-flops, or may be asynchronously preset/reset to desired logic states. These features are all controllable through on-chip programmable circuitry.

Abstract: A semiconductor memory cell for a programmable read-only memory includes a polysilicon layer formed with laterally spaced surface regions which differ in impurity concentration and which form two back-to-back series diodes functioning as a programmable diode and an isolating diode. Because of the different impurity concentration, the diodes have different reverse-bias breakdown voltages. The programmable diode has the lower reverse-bias breakdown voltage. The high reverse-bias breakdown voltage of the isolating diode has the effect of blocking the parasitic current drain on the programming current.

Abstract: In a memory cell array of the kind including a memory cell capacitor and a memory cell transistor connected in series between a field plate line and a bit line, both the field plate line and bit line are precharged to the same potential level. The field plate line is connected to one input of a sense amplifier and the bit line is connected to the other input. The charge and discharge of the memory cell capacitor causes equal and opposite voltage changes on the field plate line and bit line. With respect to prior art the cell signal is increased by the amount of signal on the field plate line and when sensed against a reference signal which is about one-half the amount of the cell signal, the sensed signal is about twice that obtainable in the prior art.

Abstract: The edge profile of a silicon layer is shaped to have a gradual incline considerably less than 90.degree. by continuously reducing the amount of oxygen mixed with carbon tetrachloride in a reactive ion etching environment. The etching mode varies from complete isotropic etching when the amount of oxygen is maximum, to complete anisotropic etching when the oxygen content is zero.

Abstract: A logic circuit in which (1) a first bipolar transistor has a base, an emitter, and a collector coupled to a voltage/current source, and (2) a second bipolar transistor has a base coupled to the emitter of the first transistor, an emitter coupled to a constant voltage source, and a collector coupled to the voltage/current source contains operational control circuitry for preventing the second transistor from either turning off or normally going into deep saturation. Each transistor is typically an NPN device. The operational control circuitry may then comprise (1) first circuitry for providing current from the voltage/current source in a single current-flow direction to the collector of the second transistor and (2) second circuitry for providing current from the first circuitry in a single current-flow direction to the base of the second transistor. Optimally, the first circuitry prevents the second transistor from ever going into deep saturation.

Abstract: A method of fabricating a thick field oxide isolation layer employs dual photoresist layers and selective ion implantation. A thick field oxide layer is grown on a silicon wafer and is covered with a negative photoresist layer followed by a thicker positive photoresist layer. The positive photoresist layer is exposed through a mask and developed to leave a portion remaining where an aperture in the field oxide is to be made. Boron ions are implanted into the silicon wafer through the layers not covered by positive photoresist. The remaining positive photoresist and the underlying negative photoresist are removed to expose the field oxide, after which the patterned negative photoresist is used as a mask to etch a hole in the field oxide that is self-aligned between the boron implants.

Abstract: An arbiter circuit includes a latch made of two crosscoupled NAND gates, one of which is a Schmitt NAND gate, a difference detector, and two output NOR gates. The output of the latch is coupled to the difference detector and to one input of the NOR gates. The NOR gates receive another input from the difference detector. The difference detector is responsive to a voltage difference that exceeds one V.sub.BE, thereby blocking signals that originate in the latch during oscillating or metastable states of the latch, which may include rut pulses.

Abstract: A method of fabricating an array of high capacity memory cells comprises patterning a semiconductor surface to form memory cell areas; covering the memory cell areas with insulator; forming an ion layer of first conductivity type throughout the insulator; forming an ion layer of second conductivity type throughout the semiconductor surface; forming a first conductive pattern over the insulating layer to form a storage gate and to define a storage region extending to an isolation region and to define a transfer region spaced from the isolation region by the storage region; removing ions of first conductivity type from the portion of insulator above the transfer region and from other active areas; removing ions of second conductivity type from the transfer region and other active areas; diffusing ions of first conductivity type from the insulating layer to the storage region to produce in the storage region a shallow ion layer of first conductivity type and a deep ion layer of second conductivity type; and form

Abstract: A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses corresponding to a limited number of previously translated logical addresses. The available space in the TLB is divided into partitions, each of which stores address translation data for a particular user process. The TLB partition in current use is identified by the value stored in a user partition counter, which is also used to verify that certain process control information (stored in a stack memory location) associated with the partition matches the process control information for that user process which is currently in control of the central processing unit.