Abstract: A heat sink assembly for securing a heat sink to a chip on a circuit board using a clip to secure the heat sink to the chip. The assembly includes a pair of support beams, a clip attached to the pair of support beams, and a heat sink. Optionally, the assembly also includes a plurality of bias members biased between the heat sink and the circuit board and a pair of positioning pins positioned between the heat sink and the circuit board. The clip is biased between the heat sink and the pair of support beams. The clip has a plate having a first end and a second end with the first end having an aperture for fastening the first end to a first support beam and the second end having a hook for fastening the second end to a second support beam. Optionally, the clip is made of spring steel and provides a downward biasing force of between about 3 psi and about 25 psi and preferably about 10 psi.

Abstract: A circuit board support operable with boards requiring a horizontal motion for engagement of connectors. The support can be exchanged for a traditional standoff and screw combination without modification of the board or supporting structure.

Abstract: A computer system (10) includes a node controller (12) operable to process invalidation requests. The node controller (12) includes a network interface unit (20), a memory directory interface unit (22), a processor interface unit (24), an input/output interface unit (26), a local buffer unit (28), and a crossbar unit (30). A local processor (16) generates an invalidation request that is processed by the processor interface unit (24) for placement into the local buffer unit (28). The invalidation request indicates that particular data within a local memory (18) associated with the node controller (12) has been altered by the local processor (16). The local buffer unit (28) generates a plurality of invalidation messages in response to the invalidation request, the invalidation messages being destined for remote processors (16) associated with remote node controllers (12) in the computer system (10) that share the particular data.

Abstract: A system and method for inexpensively detecting preempted execution entities such as threads without kernel involvement. In a computer system having a memory and one or more processors, a shared memory arena is formed in user space within the memory. A preempt bit vector is then formed within the shared memory arena such that the preempt bit vector is accessible to any of a plurality of execution entities running in user mode. The preempt bit vector includes a plurality of rbits, wherein each rbit is associated with one of the plurality of execution entities and wherein an rbit is marked whenever its associated execution entity is preempted. Detection of preempted threads then becomes a matter of reading, via program code executing in user mode on one of the plurality of processors, bits in the preempt bit vector to detect preempted execution entities.

Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Abstract: A system that includes a pop-up graphical user interface that includes menu bars overlapping marking menu zones. The interface pops up at the current position of the cursor when the space bar is held down. The menu bars are positioned around a central marking zone with the common menu bars located above the central zone and task specific menu bars located below the central zone. The common application menu bar is positioned outer most and the common window menu bar is located inner most. The menu bars are sized in a “stair-step” pattern and the commands therein are left and right justified to fill the menu bar evenly. The menu bar menu items are accessed just like menu bar items typically found at the top of windows. The menu bars mimic the menu bars that a user may need to use during tasks that users typically perform using the menu bars found in application windows.

Abstract: A system and method of cooling heat generating components. Heat generating components are placed in an enclosure having an air permeable cover. A mating panel having a mating connector is placed proximate to the air permeable cover. A fan assembly having a hub is coupled to the mating panel, wherein coupling includes wiring the fan to a fan connector, mounting the fan connector along an axial line running through the hub and pressing the fan assembly into the mating panel so as to mate the mating connector and the fan connector.

Abstract: A system and method are provided for automatically capturing a graphics session so that the session can be subsequently re-created in a precise manner. In some embodiments, the image data produced by the rendering process is recorded and stored in a memory medium. The image data can then be used to re-create the images produced by the original rendering process. The image data can be collected through a connection at the graphics processing host, at the client computer from which the graphics session is controlled, or at an intermediate point. In other embodiments, the initial state of the graphics processing host is captured, where the initial state includes the graphics data to be rendered. In addition, commands sent to the graphics processing host to control the graphics session are also captured. These commands are typically sent by the client computer from which the session is controlled.

Abstract: A bridge device (12) in a computer system interconnects with peripheral component interconnect (PCI) devices (14) over a PCI bus (16). The bridge device (12) includes a plurality of read response buffers (10) to provide data to the PCI devices (14). Each of the read response buffers (10) has a plurality of counters/registers (22) associated therewith. The counters/registers (22) measure various parameters associated with the request and retrieval of requested data and speculative data through the read response buffers (10). In response to the parameters measured by the counters/registers (22), the read response buffers (10) can be optimally allocated among the PCI devices (14).

Abstract: A computing device (12) includes a first process (16) and a second process (18) executing thereon in conjunction with a local memory (20). The local memory (20) stores data files retrieved from a database (14). The database (14) maintains the data files in page formats. Each page (22) maintained within the database (14) includes a counter location (24). The first process (16), desiring to write access a particular page (22), increments the counter location (24). The counter location (24) provides an indication that the contents of the particular page (22) are not valid. The second process (18), desiring to read or write access the particular page (22), determines that the particular page (22) is not in a valid state according to the counter location (24). The first process (16), upon terminating write access to the particular page (22), increments the counter location (24). The counter location (24) now provides an indication that the contents of the particular page (22) are in a valid state.

Abstract: A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request.

Abstract: An aspect of interconnect design for optimizing delay characteristics of interconnects. The interconnect design for delay characteristics optimization is performed using a method for optimizing repeaters positioning along interconnects. The method includes inserting repeaters in positions along a first interconnect at predetermined intervals that are related to signals transition time. The method further includes inserting repeaters in positions along a second interconnect at the predetermined intervals, the second interconnect being a neighbor of the first interconnect. The positions of repeaters along the second interconnect are offset, by a predetermined length, relative to the positions of repeaters along the first interconnect so that the repeaters positions along the second interconnect are shifted relative to the repeaters positions along the first interconnect. In one embodiment, the predetermined length is half (0.

Abstract: A computer-based method for determining a property of a location on a computer surface model where the location is described by a set of parameters and the surface model is described by a set of control vertices having a corresponding set of subdivision rules, and the control vertices admit a parameterization of regular sets of control vertices, includes receiving input specifying coordinates of control vertices that describe the surface model, projecting the specified coordinates of the control vertices into an eigenspace derived from a matrix representation of the subdivision rules to produce a set of projected control vertices, determining which of a hierarchically nested set of regular tiles of the surface model contains the location, and evaluating the location as a function of a valence of one of the control vertices, the determined nested tile, and the set of projected control vertices. The evaluated location is stored in a computer memory.

Abstract: A system that predistorts a computer generated paint stamp for paint being applied to a 3D computer model of an object. The predistortion is based on a difference in shape and orientation of a texture space polygon, to which the stamp is initially applied, and the corresponding world space target polygon of the model. Because the paint stamps often overlap several polygons of different shapes and orientations, the distortion compensation becomes a weighted average of the distortion compensation for the polygon under the stamp and its nearest neighbors.

Abstract: A memory protection system for shared memory in a multiprocessor computer is provided that comprises a multiprocessor computer (10) having a plurality of processor regions and a plurality of memory pages (16). Each processor region includes one or more processors (12). Each processor (12) includes a cache (18), and each memory page (16) includes one or more cache lines (20) for coupling to the cache (18) of processors (12) within the plurality of processor regions using the memory page (16). Each memory page (16) includes a set of protection bits (82) associated with each processor region in the plurality of processor regions. The set of protection bits (82) includes an acquire protection bit (84) for each processor region in the plurality of processor regions. The acquire protection bit (84) determines whether the associated processor is enabled to perform acquire operations on the memory page (16).

Abstract: A peripheral wrapper having a wrapper frame for enclosing the computer peripheral. The frame includes a first end for containing a connecting end of the computer peripheral. The wrapper includes a clip or gripping member attached to the frame near the second end of the frame, wherein the clip for grippedly and removably couples the frame to a dock section of a computer peripheral container chassis. The clip has a first leg coupled to the frame and a second leg generally parallel to first leg, the second leg not coupled to the frame. The second leg having a spring force towards the first leg when the clip is engaged to an edge of the chassis dock so that the clip is grippedly and removably attached to the chassis dock. In one embodiment, the clip includes a damping material located between the frame and the chassis dock. Another aspect of the present invention provides a computer peripheral modular system including a chassis having at least one dock.

Abstract: An electronic design guide, such as a french curve, can be placed in the geometry layer of a drawing program. This allows the design guide and a drawing tool, such as an electronic paint brush, to be moved about with in the drawing simultaneously using two different input control devices, such as a mouse and an electronic stylus/tablet. The design guide can then be used block or mask paint from being applied to the drawing by comparing the coordinates of the cursor with the area of the guide and setting pixels of the drawing accordingly. The masking can be performed even as the guide is moved. The system also can be set to constrain the path of the ink applied by the drawing tool to the edge of the drawing guide even as the guide is moved. As the cursor is moved the position of the cursor is matched with the closest next line segment of the guide and that portion painted.

Abstract: A method, system, and computer program product for a new data visualization tool for determining distribution weights that represent values of a categorical variable and then mapping a distinct color to each of the weights so as to visually represent the different values of the categorical variable (or data attribute) in a scatter plot. The distinct colors of a splat are based on the distribution of categorical variable values in a corresponding bin, the distribution of which is represented by a vector. The vector contains as many locations as the number of different values for the categorical variable. The value stored in each location is typically a weight or percentage for that particular value of the categorical variable. Each location in the vector is also associated with a distinct color.

Abstract: A system for color balancing within a liquid crystal flat panel display unit. The present invention includes a method and system for altering the brightness of two or more light sources, having differing color temperatures, thereby providing color balancing of a liquid crystal display (LCD) unit within a given color temperature range. The embodiments operate for both edge and backlighting systems. In an embodiment, two planar light pipes are positioned, a first over a second, with an air gap between. The first light pipe is optically coupled to receive light from a first light source having a color temperature above the predetermined range and the second light pipe is optically coupled to receive light from a second light source having a color temperature below the predetermined range.

Abstract: A system and method for cooling individual electronic components utilizes individual manifolds to create individual flows of a negatively pressurized cooling fluid. This permits components with significantly different cooling loads to be located immediately adjacent each other on a circuit board, but without loss of space and computation time efficiencies, because cooling the components individually avoids heat generated by each component from adversely affecting the performance of the cooling system for adjacent components. A heat sink can be coupled to the components for increased heat transfer, and a preferred design of heat sink both dissipates heat and directs the flow of the fluid in an optimum manner.