Abstract: A method and apparatus provide for preserving hardware resources in connection with a display of complex scenes. Polygons which make up portions of the display can be culled prior to use of the hardware resources. An occlusion parameter for use in the culling operation can be determined in accordance with a monitoring of a plurality of tiles which constitute a display. In particular, a maximum depth value associated with a given tile can be utilized to indicate whether a subsequently received polygon or primitive would otherwise be occluded and should therefore be discarded or ignored rather than rasterized.

Abstract: The invention provides a method for performing computer graphic simulation of an anisotropic surface reflecting light towards a viewer. First, the data necessary to calculate the amount of light reflected from each point of the anisotropic surface toward the viewer is obtained. This data includes a statistical description of the surface, as well as information about the light and its directions of incidence and reflection. The data is then sent to a renderer, which calculates the amount of light reflected from each point of the anisotropic surface toward the viewer. An image is then created, based on the calculated values. The calculation step is performed with the aid of a model that is derived from wave physics. The model also relies on a statistical, probabilistic description of the anisotropic surface, a description which treats the height of any given point on the surface as a random variable.

Abstract: A multiple light source flat panel liquid crystal display (LCD) system having enhanced backlight brightness and specially selected light sources. According to the present invention, brightness in the LCD is enhanced by polarization recycling using a pre-polarizing film to pre-polarize light, and a special reflector for recycling light reflected by the pre-polarizing film. In one embodiment, the pre-polarizing film comprises a layer of DBEF brightness enhancement film, and the rear reflector is made of a PTFF material. In another embodiment, the rear reflector is covered with a film comprising barium sulfate. The multiple light sources are selected such that, at any color temperature within a predetermined range, the brightness of the LCD is not reduced below a given threshold minimum (e.g., 70 percent of the maximum brightness).

Abstract: A low cost high performance three dimensional (3D) graphics system can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a color television set. The richly featured high performance low cost system gives consumers the chance to interact in real time right inside magnificent virtual 3D worlds to provide a high degree of image realism, excitement and flexibility. An optimum feature set/architecture (including a custom designed graphics/audio coprocessor) provides high quality fast moving 3D images and digital stereo sound for video game play and other graphics applications.

Abstract: In a computer system including a processor coupled to a memory via a bus, a system for a reduced instruction set graphics processing subsystem. The graphics processing subsystem is configured to accept graphics data from a computer system via a bus. The graphics processing subsystem is deeply pipelined to achieve high bandwidth, and is operable for processing graphics data including a first and second set of graphics instructions. The graphics instructions from the second set are more complex than the graphics instructions from the first set. The graphics processing subsystem also includes a built-in recirculation path for enabling the execution of graphics instructions by multi-pass. The graphics pipeline is streamlined such that the graphics instructions from the first set are processed efficiently. The graphics instructions from the second set are processed by using multi-pass via the recirculation path.

Abstract: In a computer graphics system, a level of detail value is determined by calculating the maximum absolute difference between values of s and t coordinates of pixels diagonally adjacent to each other within a quad of pixels. In particular, the texels needed for the quad of pixels for each of two integer levels of detail surrounding the calculated diagonal level of detail are virtually guaranteed to be within a 4×4 footprint of texels projected into a texture memory. In addition, the texture value is determined by interpolating between 2 integer levels of detail without aliasing.

Abstract: A method, system, and computer program product are provided for fast computation using parallel resampling and blending in multi-channel texture mapping. In one embodiment, slices of projection data for volume rendering are loaded into multiple textures. The loaded textures are combined using multi-channel texture mapping to obtain a multi-channel data frame for storage in a multi-channel frame buffer. The multiple textures are combined using a texture mapping operation that includes a linear blending operation, such as, a maximum, minimum, and/or sum blending operation. Multi-channel frame buffer data is then aggregated to obtain a final single channel grey-level output of pixel data. In one example implementation of the present invention, a load unit loads slices of projection data into multiple textures. A multi-channel texture engine combines the multiple textures to obtain multi-channel frame data for storage in a multi-channel frame buffer.

Abstract: The present invention pertains to an apparatus for and method of mapping texture memory to a texture cache such that cache contention is minimized. Significantly, in one embodiment of the present invention, addresses of the texture memory are mapped to entries of the texture cache according to a predetermined hashing scheme. According to the one embodiment, texture memory is addressed as a virtually contiguous address space by a multi-dimensional index. The multi-dimensional index is further partitioned into a low order bit field and a high order bit field. Low order bits of the multi-dimensional index are directly mapped to low order bits of the cache address. High order bits of the multi-dimensional index are mapped to high order bits of the cache address according to a predetermined address-hashing scheme. Particularly, in one embodiment, high order bits of the multi-dimensional index are selectively “exclusive-or-ed” to generate corresponding addresses of the texture cache.

Abstract: A multiple counter-rotating ring computer network system having a permission control scheme for client isolation. The peripheral channel allows two rings to be folded into one longer ring so that faulty nodes can be effectively removed from the network. Or, any of the rings can be masked so that they are unoperational. The network system also allows several client isolation states ranging from complete isolation to master access. These types of isolation allow faulty client devices to be tested while maintaining a high-level of network security by configuring the client to an appropriate isolation state.

Abstract: Planar texture maps which reflect the distances and angles of a 3-D surface are generated. A user is permitted to manually adjust the balance between discontinuity and distortion. The user selectively modifies the 3-D surface, and by doing so adjusts the balance between discontinuity and distortion in the planar map. Each point on the 3-D surface corresponds to a unique point on the planar map. Operations may therefore be performed on the simpler 2-D planar map rather than the more complex 3-D map, and the result of the operations may be uniquely mapped to the 3-D surface. Further, the majority of the vertices on a 3-D surface are mapped automatically, even though the user maintains a high degree of control over the mapping process via altering the 3-D surface boundary. User-selected map vertices may be pinned to a user-selected location, and held fixed while a conventional relaxation technique is applied. This provides the user with a greater degree of control over the relaxation process.

Abstract: A view port comprising an oblique slice intersecting a stack of textured images is defined. A polygon associated with the view port slice is divided into multiple polygons, wherein each polygon is clipped to the surface of each intersecting texture. Each intersecting texture is then enabled, one at a time. When each texture is enabled, each polygon intersecting with the enabled texture is drawn. The colors of the vertices that fall within the active textures are maintained according to the color of the active texture, and the colors of the vertices that fall within the inactive texture are set to zero. This process is repeated until all of the intersecting textures have been enabled. This causes each polygon to be drawn exactly twice. Additive blending is enabled so that the first and second polygons are blended together. When each polygon is drawn, bi-linear interpolation techniques are used to fill-in the colors of the texels that lie in between the vertices of the polygon.

Abstract: A scalable multiprocessor system includes processing element nodes. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an n-dimensional topology, and routers for routing messages between the processing element nodes on the physical communication links. The routers are capable of routing messages in hypercube topologies of at least up to six dimensions, and further capable of routing messages in at least one n dimensional torus topology having at least one of the n dimensions having a radix greater than four, such as a 4×8×4 torus topology.

Abstract: The method and apparatus employ a texture filter in a graphics processor to perform a transform such as, for example, a Fast Fourier Transform. The texturizer can include an array of linear interpolators. The architecture reduces the computational complexity of the transform processes.

Abstract: In a computer system, a method for determining an optimal loop interchange, set of register tiling amount, and cache tiling size for compiling source code into object code. The method first constructs a model of the specific computer system upon which the object code is to be run. Next, the search space comprising all of the different possibilities of the loop interchanges, register tiling amounts, and cache tiling sizes is run through the model to determine estimated times of execution. The particular loop interchange, set of register tiling amounts, and cache tiling sizes corresponding to the best estimated time of execution is then selected as being the most optimal. The source code is then compiled according to this optimal loop interchange, register tiling amount, and cache tiling size.

Abstract: A system and method for encoding N signals onto an N+1 conductor signal line. First, the electrical characteristics of the signal line are determined by calculating an inductance matrix for each conductor, calculating electrostatic inductance for each conductor and calculating an eigen-mode encoding matrix. The N signals are then encoded into signals enc(0) through enc(n), wherein the step of encoding comprises the step of encoding each of the N signals as a function of the eigen-mode encoding matrix.

Abstract: A computer-implemented method for generating three dimensional line drawings in which only silhouette edges and true edges that are visible are displayed. The color, depth, and stencil buffers are respectively initialized to background color, farthest value, and zero. In a first pass, all polygons are rendered by filling all pixels within their boundaries. At each pixel, only its depth value is modified by selecting the nearer of either the current depth value or the new depth value. This creates a depth image in the depth buffer used for occlusion detection. In a second pass, all the polygons of a particular orientation are rendered by drawing lines from vertex to vertex for each of the polygons. The pixel values are modified only when the depth comparison passes (i.e., the pixel is visible and not occluded). Each time a particular pixel is modified, its corresponding stencil value is toggled from 0 to 1 or from 1 back to 0.

Abstract: A method and system for efficient translation of memory addresses in computer systems. The present invention enables address translations between different address spaces to be performed without using the table lookup step typically required in the prior art. Thus, the present invention provides significant improvements in both time and space efficiency over prior art implementations of address translation. In modern computer systems where direct memory access (DMA) operations are used extensively, especially in the emerging field of operating system (OS) bypass technology, the performance improvements afforded by the present invention are particularly critical to the realization of an efficient and high performance system. A method and system for efficiently translating memory addresses in computer systems and the address representation used are described herein.

Abstract: A collaborative work environment supports manipulating an object defined by a three-dimensional model by multiple remote participants. A three-dimensional model of the object is able to be translated, rotated and scaled in a work area of a whiteboard associated with the collaborative work environment. Each of the remote participants is able to view, manipulate, and mark-up the three-dimensional model of the object so that the remote participants can work collaboratively together.

Abstract: A novel technique for decoding variable length encoded data in a bit stream such as video data compressed in accordance with JPEG, MPEG, or DV standards is disclosed. The disclosed technique preprocesses the input data to generate a pointer to a variable length code table from the encoded code word, the entry in the variable length table providing the information necessary to decode the code word. Preprocessing of the input data includes encoding leading ones or leading zeros and selecting a subset of bits following the leading ones or zeros. The pointer to the variable length code table is generated from a base value corresponding to the symbol type being decoded. The base values for the symbols being decoded may be stored in a first look up table which may contain multiple entries for one or more of the symbol types, the number of entries corresponding to the number of leading ones or zeros.

Abstract: Improved method and apparatus for facilitating fast barrier synchronization in a parallel-processing system. A single input signal and a single output signal, and a single bit of state (“barrier_bit”) is added to each processor to support a barrier. The input and output signal are coupled to a dedicated barrier-logic circuit that includes memory-mapped bit-vector registers to track the “participating” processors and the “joined” processors for the barrier. A “bjoin” instruction executed in a processor causes a pulse to be sent on the output signal, which in turn causes that processor's bit in the dedicated barrier-logic circuit's “joined” register to be set.