Patents Assigned to Silicon Laboratories
  • Antenna diversity system with frame synchronization
    Patent number: 8548031
    Abstract: A tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor synchronizes the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset. The digital signal processor performs a selected antenna diversity operation on the first and second DSP frames to produce an output signal.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: October 1, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Younes Djadi, Russell Croman, Scott Thomas Haban, Javier Elenes
  • ADAPTIVE TRIAC CONTROLLER
    Publication number: 20130249604
    Abstract: A low voltage AC power controller uses a line coupled capacitor AC to DC converter circuit to obtain energy from AC line power supplied to an AC load and may be used with an external high voltage AC switching device to control power supplied to the AC load. The line coupled capacitor AC to DC converter circuit provides a low power device that senses characteristics of the power supplied to the load and can communicate sensed information and/or receive control information related to the power supplied to load.
    Type: Application
    Filed: December 31, 2012
    Publication date: September 26, 2013
    Applicant: Silicon Laboratories Inc.
    Inventor: Eric B. Smith
  • Analog to digital converter
    Patent number: 8542144
    Abstract: An analog to digital converter converts an input analog signal to a digital representation using successive approximation logic to generate a plurality of digital values approximating the analog signal. Evaluation logic evaluates each of the digital values by converting each of the digital values in a digital to analog converter (DAC) to a DAC analog signal and comparing the DAC analog signal to the input analog signal to determine a comparison result used by the successive approximation logic to generate a next one of the digital values. An evaluation time period for one or more bits of the digital representation is longer than for one or more other bits in the digital representation. The DAC includes a resistor ladder. Reference voltages of the DAC are increased for evaluation of the least significant bit (LSB) to obtain more accurate results without increasing a number of resistors.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 24, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Abdulkerim L. Coban
  • Method and apparatus for controlling a harmonic rejection mixer
    Patent number: 8543077
    Abstract: In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 24, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Aslamali A. Rafi, Alessandro Piovaccari
  • Performing power control in a receiver based on environmental noise
    Patent number: 8538365
    Abstract: In one embodiment, a method includes receiving and processing an incoming radio frequency (RF) signal in a receiver. Based on this signal, an environmental noise level can be determined, where this level corresponds to environmental noise present in an environment in which the receiver is located. Then, if the environmental noise level is substantially greater than receiver-generated noise, power consumption of at least one analog front end component of the receiver can be reduced.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Russell Croman, Christopher S. Gregg, Dan B. Kasha, Michael R. May, John Khoury, Javier Elenes
  • Rotating harmonic rejection mixer
    Patent number: 8538366
    Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: September 17, 2013
    Assignee: Silicon Laboratories Inc
    Inventor: Aslamali A. Rafi
  • Combined complex real mode delta-sigma ADC
    Patent number: 8531325
    Abstract: A delta-sigma analog-to-digital converter (ADC) is disclosed. In one embodiment, the delta-sigma ADC includes a dual mode resonator and a plurality of switches. The delta-sigma ADC is configured to operate in a real modulation mode or a complex modulation mode based on settings of the plurality of switches.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Péter Onódy
  • Direct digital interpolative synthesis
    Patent number: 8531246
    Abstract: A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Yunteng Huang
  • Digital hold in a phase-locked loop
    Patent number: 8532243
    Abstract: A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Srisai R. Seethamraju, Jerrell P. Hein, Kenneth Kin Wai Wong, Qicheng Yu
  • Quadrature signal generation in radio-frequency apparatus and associated methods
    Patent number: 8532236
    Abstract: A radio-frequency (RF) apparatus, which may reside in a receiver or transceiver, includes receive-path circuitry. The receive-path circuitry includes a poly-phase filter and a harmonic filter. The poly-phase filter accepts an input signal and generates two output signals. One output signal of the poly-phase filter constitutes an in-phase (I) signal. The other output signal of the poly-phase filter constitutes a quadrature (Q) signal. The a harmonic filter couples to the poly-phase filter. The harmonic filter accepts as input signals the in-phase and quadrature output signals of the poly-phase filter.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Donald A. Kerth
  • Integrated low-IF terrestrial audio broadcast receiver and associated method
    Patent number: 8532601
    Abstract: An integrated low-IF (low intermediate frequency) terrestrial broadcast receiver and associated method are disclosed that provide an advantageous and cost-efficient solution. The integrated receiver includes a mixer, local oscillator generation circuitry, low-IF conversion circuitry, and DSP circuitry. And the integrated receiver is particularly suited for small, portable devices and the reception of terrestrial audio broadcasts, such as FM and AM terrestrial audio broadcast, in such portable devices.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: G. Tyson Tuttle, Dan B. Kasha
  • Controlling power consumption in a radio tuner
    Patent number: 8526897
    Abstract: According to one aspect of the present invention, a controller is coupled to at least first and second signal processors (at least one of which includes analog demodulation circuitry and another of which includes digital demodulation circuitry). The controller may operate to disable the first signal processor responsive to a control signal that indicates that a second signal (corresponding to a demodulator output) is available from the second signal processor.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 3, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Matthew Henson
  • Transceiver having multiple signal processing modes of operation
    Patent number: 8521099
    Abstract: A transceiver includes a processor, which is adapted to in a transmit mode of the transceiver, form at least part of a transmitter and in a receive mode of the transceiver, form at least part of a receiver. The transceiver may include at least one analog-to-digital converter to provide digital signals to the processor in both the transmit and receive modes of operation; and the transceiver may include at least one digital-to-analog converter to receive digital signals from the processor in the transmit and receive modes of operation. The processor may be fabricated on an integrated circuit with at least one of the analog-to-digital converters and/or with at least one of the digital-to-analog converters.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 27, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Lawrence Der, George Tyson Tuttle, Alessandro Piovaccari, Chunyu Xin, Scott Haban, Javier Elenes, Dan Kasha, Peter Vancorenland
  • Circuit for ESD protection including dynamically terminated diode strings comprised of bipolar devices
    Patent number: 8520347
    Abstract: An integrated circuit includes a plurality of terminals, an unterminated diode string formed from a plurality of P-N junction devices arranged in series and coupled to the plurality of terminals, and a plurality of switches. Each of the plurality of switches includes a first terminal coupled to an anode of one of the plurality of P-N junction devices and a second terminal coupled to a power supply terminal, and is controllable to selectively couple the anode to the power supply terminal in response to an ESD event. The plurality of switches configured to dissipate an ESD current associated with the ESD event and dynamically terminate the unterminated diode string at a node where the ESD current falls below a turn-on threshold of a next P-N junction device in the unterminated diode string.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: August 27, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Jeremy Charles Smith
  • Performing testing in a radio device
    Patent number: 8515416
    Abstract: In a radio device such as a receiver or transceiver, a test operation can be performed to determine performance. A received signal can be processed to obtain demodulated samples, which can be provided to a logic to perform a logic operation on the samples to generate a logic output. A storage such as a counter or other mechanism is coupled to the logic to store a count of a number of the logic outputs having an error.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Silicon Laboratories Inc
    Inventor: Hendricus De Ruijter
  • Integrated circuit, micro-controller unit, and method including a synchronous sampling controller
    Patent number: 8513989
    Abstract: A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: August 20, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Bradley Martin, Thomas Saroshan David, Alan Lee Westwick
  • Sigma-delta modulation with reduction of spurs using a dither signal
    Patent number: 8514118
    Abstract: A method includes operating on a sigma-delta modulated signal to reduce a dither signal component in one of a first signal and a second signal, the first signal being an integer portion corresponding to a digital frequency ratio and the second signal corresponding to a fractional portion of the digital frequency ratio. In at least one embodiment of the method, the operation is performed digitally in a frequency synthesizer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 20, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Adam B. Eldredge
  • Apparatus for providing reference signals and associated methods
    Patent number: 8515373
    Abstract: An apparatus includes a signal processing circuit and at least two oscillators that provide, respectively, at least first and second reference signals. The apparatus further comprise a selection circuit. The selection circuit provides to the signal processing circuit one of the first and second reference signals depending on a mode of operation of the signal processing circuit.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 20, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Hendricus de Ruijter, Sharon Mutchnik
  • Integrated CMOS porous sensor having sensor electrodes formed with the interconnect conductors of a MOS circuit
    Patent number: 8507954
    Abstract: A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ?? A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: August 13, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Timothy Cummins
  • Amplifier using master-slave control scheme
    Patent number: 8508298
    Abstract: Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 13, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Pavel Konecny, Jinwen Xiao