Patents Assigned to Societe pour L'Etude et la Fabrication de Circuits Integres Speciaux EFCIS
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Patent number: 4805759Abstract: In an installation for conveying delicate objects such as semiconductor layers during processing operations and for handling such objects in a controlled atmosphere, wheeled carriages are drawn along tracks by an endless belt and are not driven by motors in order to satisfy conditions of cleanliness and freedom from pollution hazards. By means of transfer tools, object-holding cassettes are taken from the carriages during operation and replaced on the carriages after processing in the different machines.Type: GrantFiled: December 8, 1986Date of Patent: February 21, 1989Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux EFCISInventors: Andre Rochet, Guy Dubois, Louis Faure, Alain Lalanne
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Patent number: 4780429Abstract: In a method of fabrication of field-effect transistors having very small dimensions, the gate electrode is formed by a first layer of metallic silicide. Insulating embankments are formed along the lateral edges of the gate and a second layer of metallic silicide is then deposited so as to form the source and drain electrodes. At locations in which the second layer covers the first, planning by planarizing etching is performed so as to produce a structure of flat electrodes in which the gate is separated from the source and drain electrodes by a smaller interval than would be possible in the case of separation by photoetching.Type: GrantFiled: January 12, 1987Date of Patent: October 25, 1988Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux EfcisInventors: Alain Roche, Joseph Borel, Annie Baudrant
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Patent number: 4721865Abstract: The invention relates to a detector of the mean level of a signal particularly intended to indicate whether an expected alternating signal is absent or present. This detector uses an analog comparator, a digital counter and a converter for establishing an analog signal to be compared with the expected rectified signal. The counter content oscillates round the mean value of the rectified signal. The counter serves as a digital integrator for the sign of the difference between the input signal and the content of the counter, in such a way that on average the input signal is just as often above as below the counter content. The digital - analog conversion can take place with the aid of switched capacitors.Type: GrantFiled: September 18, 1985Date of Patent: January 26, 1988Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux - EfcisInventors: Louis Tallaron, Jean C. Bertails
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Patent number: 4628472Abstract: The invention provides a high-speed binary multiplier.The binary digits x.sub.i of the multiplicand X and y.sub.j of the multiplier Y (in two complement form) are converted by respective coders into coefficients a.sub.i and b.sub.j such thatX=a.sub.m-1 2.sup.m-1 + . . . a.sub.1 2.sup.1 +a.sub.oY=b.sub.n-1 2.sup.n-1 + . . . b.sub.1 2.sup.1 +b.sub.owhere a.sub.i and b.sub.j can only assume three values 0,1 or -1 and where two consecutive coefficients a.sub.i and a.sub.i-1 and b.sub.j or b.sub.j-1 cannot both be non zero. a.sub.i and b.sub.j are each represented by a pair of binary logic signals (r.sub.i,u.sub.i) or (s.sub.j,v.sub.j). The signals (s.sub.j,v.sub.j) serve for controlling a routing circuit which further receives as signals to be routed the signals (r.sub.i,u.sub.i) for directing these signals, depending on the values of coefficients b.sub.j, to the appropriate inputs of an adder stage operating without carry-over propagation. The outputs of this adder are reconverted into binary form by a decoder.Type: GrantFiled: November 18, 1983Date of Patent: December 9, 1986Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux-Efcis.sup.2Inventor: Thierry Fensch
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Patent number: 4599575Abstract: In order to diminish the risk of oscillation of a broad-band amplifier 20 MHz without considerably reducing the product gain x bandwidth, this amplifier comprises a differential stage T1, T2, T3, T4, a follower stage T5, T6, two common mode feed-back braches T8, T9, T5 on the one hand, T11, T12, T10, on the other hand, and compensation capacitors C1, C2 that are unbalanced, C2 higher than C1, between the supply terminal B and each of the outputs S1, S2 of the differential stage.Type: GrantFiled: April 3, 1985Date of Patent: July 8, 1986Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux EfcisInventor: Patrick Bernard
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Patent number: 4459542Abstract: A spectrum analyzer comprises a plurality of filters each provided with a low-pass output and a high-pass output both having the same cutoff frequency which is different in the case of the different filters. Switching means are provided for periodically connecting pairs of filters in cascade during a first time interval between one input for signals to be analyzed and a filtered-signal transmission channel assigned to each pair of filters. One of the filters of each pair has a high-pass (or respectively low-pass) output connected to the input of the other filter whose utilization output is the low-pass (or respectively high-pass) output. The switching means also have the function of periodically establishing a cascade connection during a second time interval between pairs of filters which are different from the first pairs. In the case of one filter, the output utilized during the second time interval is different from the output utilized during the first time interval.Type: GrantFiled: July 9, 1982Date of Patent: July 10, 1984Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux-EFCISInventors: Christian Terrier, Christian Caillon, Daniel Barbier, deceased
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Patent number: 4356055Abstract: A process and device for plasma etching a thin layer. The process includes the steps of identifying a plateau in gas pressure that occurs slightly before the end of etching and then detecting a pressure variation (increase or decrease) from the plateau pressure. Etching is stopped at a predetermined time interval after the variation following the plateau begins. The device includes one or more pressure sensors and means for determining the plateau and subsequent pressure variation.Type: GrantFiled: July 22, 1981Date of Patent: October 26, 1982Assignee: Societe pour L'Etude et la Fabrication de Circuits Integres Speciaux EFCISInventor: Michel Montier