Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.

Abstract: A method can be used to process an initial set of data through a convolutional neural network that includes a convolution layer followed by a pooling layer. The initial set is stored in an initial memory along first and second orthogonal directions. The method includes performing a first filtering of the initial set of data by the convolution layer using a first sliding window along the first direction. Each slide of the first window produces a first set of data. The method also includes performing a second filtering of the first sets of data by the pooling layer using a second sliding window along the second direction.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: A distance from an apparatus to at least one object is determined by generating a first signal and generating light modulated by the first signal to be emitted from the apparatus. Light reflected by the at least one object is detected using a Time-of-flight detector array, wherein each array element of the Time-of-flight detector array generates an output signal from a series of photon counts over a number of consecutive non-overlapping time periods. The output signals are compared to the first signal to determine at least one signal phase difference. From this at least one signal phase difference a distance from the apparatus to the at least one object is determined.

Abstract: A method and apparatus for adaptive rectification for preventing current inversion in motor windings are provided. In the method and apparatus, first and second half bridges of a plurality of half bridges are operated to synchronously rectify and permit passage of current, through the windings of the motor, in a first direction. A change of direction of the current from the first direction to a second direction opposite the first direction is detected. In response to detecting that the current changed direction to the second direction, the first and second half bridges of the plurality of half bridges are operated to quasi-synchronously rectify and block passage of the current through the windings in the second direction.

Abstract: A temperature sensing circuit includes a current generation circuit generating an initial current proportional to absolute temperature (Iptat), and a voltage generation circuit configured to mirror Iptat using an adjustable current source to produce a scaled current and to source the scaled current to a first terminal of a resistor to produce a reference voltage at the first terminal. A second terminal of the resistor has a voltage complementary to absolute temperature (Vctat) applied thereto. An analog-to-digital converter (ADC) has a reference input receiving the reference voltage, and a data input receiving Vctat or an externally sourced voltage. The ADC generates an output code indicative of a ratio between: a) either Vctat or the externally sourced voltage, and b) the reference voltage. A digital circuit determines a temperature readout from the output code and calibrates the reference voltage and the temperature readout determination based upon the output code.

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

Abstract: A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.

Abstract: An image sensor includes a plurality of pixels, where each of the plurality of pixels includes a photodiode. The image sensor is configured to capture images of a scene exposed with a flickering light source by for each of the plurality of pixels, acquiring a value representative of a light level at a corresponding pixel by gradually varying a value of sensitivity of the corresponding pixel.

Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.

Abstract: An embodiment method comprises receiving a satellite signal in a tracking channel, generating a set of replicas of a pseudo random noise sequence, comprising a punctual replica and a plurality of replicas that are different in time with respect to the punctual replica over a given time spacing, correlating the received signal with each replica to obtain amplitude correlation values, monitoring the tracking channel to detect a spoofed signal by generating a further plurality of replicas of the pseudo random noise sequence having a respective time spacing greater than the given time spacing, correlating the received signal of the tracking channel with each further replica to obtain further amplitude correlation values, calculating a shape anomaly factor based on the further correlation amplitude values, verifying the shape anomaly factor is greater than a given shape anomaly threshold, and signaling detection of a spoofed signal on the tracking channel.

Abstract: In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.

Abstract: According to one aspect provision is made of a method for ion implantation in a semiconductor wafer placed in an implantation chamber under vacuum, the semiconductor wafer having an integrated circuit area and a peripheral area around this integrated circuit area, the ion implantation allowing to apply a doping in regions, called implantation regions, of the integrated circuit area, the method comprising: forming a photosensitive resin coating serving as a mask on the semiconductor wafer, then forming openings in the photosensitive resin coating at said implantation regions of the integrated circuit area and at least at one region of the peripheral area, then implanting ions in the semiconductor wafer.

Abstract: A microelectromechanical system (MEMS) accelerometer sensor has a mobile mass and a sensing capacitor. To self-test the sensor, a test signal having a variably controlled excitation voltage and a fixed pulse width is applied to the sensing capacitor. The leading and trailing edges of the test signal are aligned to coincide with reset phases of a sensing circuit coupled to the sensing capacitor. The variably controlled excitation voltage of the test signal is configured to cause an electrostatic force which produces a desired physical displacement of the mobile mass. During a read phase of the sensing circuit, a variation in capacitance of sensing capacitor due to the actual physical displacement of the mobile mass is sensed for comparison to the desired physical displacement.

Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

Abstract: A power switch current sensing circuit includes matching first and second transistors having sources connected to first and second terminals, respectively, of the power switch. A current mirror has a first node coupled to a drain of the first transistor and a second node coupled to a drain of the second transistor. The current mirror sinks a current from the first node equal to a current flowing through the second transistor. A biasing circuit provides a same biasing voltage to the control terminals of the first and second transistors. An output resistance is coupled between the first node and a reference voltage node. A difference between a current flowing through the first transistor and the current sunk by the current mirror circuit from the first node flows through the output resistance. An output voltage produced at the first node is indicative of the current flowing through the power switch.