Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

Abstract: Uncompensated upper and lower reference-currents are generated for first and second branches of a high-frequency half-bridge within an interleaved-totem-pole PFC.

Abstract: A MEMS device includes a semiconductor body with a cavity and forming an anchor portion, a tiltable structure elastically suspended over the cavity, first and second support arms to support the tiltable structure, and first and second piezoelectric actuation structures biasable to deform mechanically, generating a rotation of the tiltable structure around a rotation axis. The piezoelectric actuation structures carry first and second piezoelectric displacement sensors. When the tiltable structure rotates around the rotation axis, the displacement sensors are subject to respective mechanical deformations and generate respective sensing signals in phase opposition to each other, indicative of the rotation of the tiltable structure. The sensing signals are configured to be acquired in a differential manner.

Abstract: The disclosure relates to a modified NFC framing is used by a reader and selected devices during at least a part of the communication between the reader and the selected devices. The reader and the selected devices store modification rules for modifying the frames. Devices not storing those modification rules will discard the received modified frames.

Abstract: A method for operating an electronic device includes while a display is in low power mode, detecting based on data collected by a time of flight (ToF) sensor, a movable object within a field of view of the electronic device; in response to the detecting initiating a period of detection having a plurality of frames, the period of detection being a time period over which a distance value indicative of a distance between the movable object and the display is detected; for each of the plurality of frames, changing the distance value to reflect whether the movable object is moving near or further from the electronic device; detecting that the distance value after the period of detection is less than a threshold distance value indicative of the movable object approaching the display; if the distance value is less than the threshold distance value, waking up the display.

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

Abstract: An electronic device includes a carrier substrate having a front face. An electronic chip is mounted on the front face of the carrier substrate and includes an optical component. An encapsulation cover is mounted on top of the front face of the carrier substrate and bounds a chamber within which the chip is situated. A front opening extends through the cover and is situated in front of the optical component. An optical element, designed to allow light to pass, is mounted within the chamber at a position which covers the front opening of the encapsulation cover. The optical element includes a central region designed to deviate the light and having an optical axis aligned with the front opening and the optical component. A positioning pattern is provided on the optical element to assist with mounting the optical element to the cover and mounting the cover to the carrier substrate.

Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.

Abstract: An array of piezoelectric micromachined ultrasound transducers (PMUTs) includes a substrate having first and second cavities buried therein. A first piezoelectric stack is carried by the substrate and at least partially overlays the first cavity. A second piezoelectric stack is carried by the substrate and at least partially overlays the second cavity. A thickness of the substrate between the second cavity and the second piezoelectric stack forms a membrane. Circuitry operates the second piezoelectric stack so as to vibrate the membrane to generate a pulse of ultrasound and to immediately subsequently operate the first piezoelectric stack to cause deformation of the second cavity which results in an increase in a resonant frequency of the membrane.

Abstract: A HEMT transistor includes: a first semiconductor layer; a gate located on a first face of the first semiconductor layer; and a first passivating layer made of a first dielectric material which extends over the said first face of the first semiconductor layer, the sides of the gate, and at least a peripheral portion of a face of the gate opposite with respect to the first semiconductor layer, wherein a second passivating layer made of a second dielectric material extends between the said face of the gate and the first passivating layer, the sides of the gate being free of the said second passivating layer.

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

Abstract: Disclosed herein is a voltage converter including input nodes configured to receive an input voltage, output nodes configured to deliver an output voltage, a rectifying bridge coupled between the input nodes and the output nodes, a capacitor and a resistor series-coupled between the output nodes, and a thyristor coupled between one terminal of the resistor and a given one of the output nodes, wherein the thyristor is configured to allow flow of a positive current from the resistor to the given one of the output nodes. A control input is configured to receive a control signal, wherein the control signal biases a gate of the thyristor to control the flow of current through the thyristor. transient voltage suppressor circuit is coupled to the gate of the thyristor, configured to activate the thyristor upon exceeding a threshold voltage.

Abstract: An etched leadframe includes separated frame portions, where each frame portion includes an intermediate region interposed between lead and die pad regions. An integrated circuit die is mounted to each die pad region. A clip is mounted to each integrated circuit die, wherein the clip includes a lead mounting portion mounted to the lead region of an adjacent frame portion and a bridge portion extending over the intermediate region of the adjacent frame portion and mounted to the die pad region of the adjacent frame portion. A first cut made through the frame portion of each etched leadframe at the intermediate region separates the lead and die pad regions without severing the bridge portion of each clip. A conductive layer is plated on full sidewalls of the lead and die pad regions exposed by the first cut. A second cut is then made through the bridge portion of each clip.

Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.

Abstract: Disclosed herein is an array of ultrasound devices. Each ultrasound device includes a first piezoelectric stack carried by a membrane and forming, together with the membrane, a first piezoelectric micromachined ultrasonic transducer (PMUT), and a plurality of second piezoelectric stacks carried by the membrane and positioned about a periphery thereof, each second piezoelectric stack forming, together with the membrane, a second PMUT. During operation, the first piezoelectric stack is configured to vibrate the membrane in response to application of an alternating voltage to the first piezoelectric stack to thereby generate at least one outgoing ultrasonic pulse toward a target, and during operation, the plurality of second piezoelectric stacks are configured to generate sense voltages in response to bending thereof induced by vibration of the membrane by incoming ultrasonic reflections off the target.

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

Abstract: A processing device includes memory circuitry having stored therein a set of weight values and a threshold value and instructions which, when executed in the processing device, cause the processing device to apply a first artificial neural network (ANN) processing to a set of sensing signals, producing as a result a set of compressed representations of the sensing signals. The first ANN processing is trained to produce the set of compressed representations using a set of training signals distributed according to a set of training classes having an integer number L of classes. The instructions further cause the processing device to configure weight values of a plurality of computing units of a set of ANN processing circuits as a function of a set of weight values.

Abstract: Disclosed herein is a method of forming a thermal sensor, including patterning an active layer on a first face of a handle substrate to form a frame, a mass carrying at least one thermally isolated MOS (TMOS) transistor, and a spring structure connecting the mass to the frame while thermally isolating the mass from the frame. The frame is then bonded to pads on a first face of an integrated circuit substrate. The handle substrate is removed, and a top cap is bonded to the first face of the integrated circuit substrate to enclose at least the mass and spring within the sealed cavity.

Abstract: A register bank includes a plurality of without-reset registers. The register bank has a write input, a write-enable input, and a write-address input coupled to the plurality of without-reset registers. The register bank has a plurality of operating modes, including an initialization mode of operation and a write mode of operation. In the initialization mode of operation, the register bank responds to receipt of a write-enable signal on the write-enable input by storing initialization data received on the write input into a register of the first plurality of without-reset registers based on a write-address signal received on the write-address input.

Abstract: A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.