Abstract: A method for manufacturing a wafer level fan-out package includes attaching a semiconductor chip on a partial area of an IO pattern formed on one surface of a wafer, forming a first passivation layer on surfaces of the semiconductor chip and the wafer, forming an RDL (redistribution layer) that is electrically conducted with the IO pattern and the semiconductor chip, in a partial area of a top surface of the first passivation layer, and forming a second passivation layer on the top surface of the first passivation layer and a partial surface of the RDL.

Abstract: Provided is a method of manufacturing a wafer level package. The method includes forming a repassivation layer that encapsulates a plurality of semiconductor chips isolated from a wafer, forming a through encapsulation via (TEV) in the repassivation layer, forming a redistribution layer electrically connected to the TEV, and forming a bump ball on the redistribution layer.

Abstract: Provided is a method of manufacturing a voice coil, and more particularly, a method of manufacturing a voice coil in which a coil pattern is formed on a wafer level package. The method includes (a) forming a first coil pattern including a first area in which a first seed metal layer is exposed upward, a second area in which a first passivation layer for forming a via hole in the first area is formed, and a third area in which a first photoresist layer is formed in a portion of the first area and the second area on an upper surface of a wafer, (b) filling an inside of the via hole formed in the first coil pattern with a conductive material and forming first coil windings, and (c) removing the first photoresist layer formed in the third area.

Abstract: Provided are a semiconductor package and a method for manufacturing a semiconductor package. The method for manufacturing a wafer-level fan-out package includes attaching semiconductor chips sawed to have a predetermined size to one surface of a wafer at predetermined intervals, forming a first passivation layer on surfaces of the semiconductor chips and the wafer, forming a redistribution layer electrically connected to the semiconductor chips on portions of an upper surface of the first passivation layer, forming a second passivation layer on the upper surface of the first passivation layer and surfaces of portions of the redistribution layer, forming external connection terminals on portions of the redistribution layer in which the second passivation layer has not been formed, and performing sawing along package boundary lines (sawing lines) and polishing the wafer to be removed such that lower surfaces of the semiconductor chips are exposed.

Abstract: Provided are a wafer level package and a manufacturing method thereof. The wafer level package method includes preparing a patterned wafer, forming a recess in a position, in which a semiconductor chip is to be attached, of the patterned wafer through an etching process, fixing the semiconductor chip to the interior of the recess, and applying a passivation material to portions other than the semiconductor chip within the recess and to an upper end of the wafer. The wafer level package includes a silicon or glass wafer including a recess formed through etching and having an area larger than a semiconductor chip, a semiconductor chip fixed to the interior of the recess, and a passivation material filling an empty space other than the semiconductor chip within the recess and applied to a portion corresponding to an area larger than the semiconductor chip on an upper end of the wafer.

Abstract: A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a via-hole pad, a second process of forming a photoresist (PR) layer on the upper surface of the PCB having the semiconductor chip and the via-hole pad, a third process of removing the photoresist layer of a remaining region except for an upper portion of the via-hole pad so that a photoresist layer of a via-hole region remains only at the upper portion of the via-hole pad, a fourth process of forming a molding layer by molding the upper surface of the PCB having the semiconductor chip to expose an upper surface of the photoresist layer of the via-hole region, and a fifth process of removing the photoresist layer of the via-hole region to form a via-hole on the via-hole pad.

Abstract: A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a via-hole pad, a second process of forming a photoresist (PR) layer on the upper surface of the PCB having the semiconductor chip and the via-hole pad, a third process of removing the photoresist layer of a remaining region except for an upper portion of the via-hole pad so that a photoresist layer of a via-hole region remains only at the upper portion of the via-hole pad, a fourth process of forming a molding layer by molding the upper surface of the PCB having the semiconductor chip to expose an upper surface of the photoresist layer of the via-hole region, and a fifth process of removing the photoresist layer of the via-hole region to form a via-hole on the via-hole pad.

Abstract: A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires.

Abstract: A semiconductor package including a first package having a first semiconductor chip, a plurality of first inner leads electrically connected to the first semiconductor chip, and a plurality of first outer leads extending from the first inner leads and electrically connected to an external apparatus; and a second package having a second semiconductor chip and a plurality of second inner leads electrically connected to the second semiconductor chip, wherein an inactive surface of the first semiconductor chip and an inactive surface of the second semiconductor chip face each other, and the first inner leads contact the second inner leads to be electrically connected to each other.

Abstract: A stacked integrated circuit package and a method for manufacturing the same are provided. The stacked integrated circuit package includes a first integrated circuit package comprising a first substrate, a first semiconductor chip, and a first molding portion, an interposer mounted on the first substrate to be electrically connected to the circuit pattern of the first substrate by a first solder bump, the interposer being provided with an opening to accommodate the first semiconductor chip, and a second integrated circuit package stacked on the first integrated circuit package and the interposer and electrically connected to the interposer by a second solder bump, the second integrated circuit package comprising a second substrate, a second semiconductor chip, and a second molding portion.

Abstract: A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.

Abstract: A method of manufacturing a semiconductor package having no chip pad includes preparing a polyimide tape on which an adhesive layer is arranged; forming lead members on the adhesive layer so as to form a plurality of semiconductor packages in a matrix form; attaching the polyimide tape to a carrier; performing wire bonding to mount semiconductor chips on the polyimide tape and connect the lead members and the semiconductor chips; forming an encapsulation member to encapsulate the semiconductor chips, the lead members, and wires; detaching the encapsulation member from the carrier and the polyimide tape; forming conductive layers each on a surface of the lead member exposed through a surface of the encapsulation member; and performing a singulation process on the encapsulation member with the conductive layers formed thereon to define unit semiconductor packages.

Abstract: A method of manufacturing a high-capacity semiconductor package includes preparing a leadframe not comprising a chip mount area and comprising only a lead on a tape; attaching an interposer on a center area of the leadframe; stacking semiconductor chips stepwise on a first surface of the interposer; performing a first wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; performing a first molding process so as to encapsulate a top surface of the leadframe, the semiconductor chips, and wires; detaching a tape from the leadframe and turning the leadframe on which the first molding process has been performed upside down; stacking semiconductor chips on a second surface of the interposer; performing a second wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; and performing a second molding process so as to encapsulate a bottom surface of the leadframe, the semiconductor chips, and wires.

Abstract: A semiconductor package including: a lead frame including a chip attachment unit and a lead unit; a semiconductor chip that is mounted on the chip attachment unit of the lead frame; a wire that electrically connects the semiconductor chip to the lead unit; an insulation layer formed in the lead frame under the chip attachment unit; and an encapsulant that seals an upper portion of the lead frame, the semiconductor chip, and the wire, wherein the lead unit does not protrude to the outside of the encapsulant.

Abstract: An integrated circuit package and a manufacturing method thereof are provided. The integrated circuit package can include a substrate provided with a circuit pattern, a first set of bonding fingers and a second set of bonding fingers, a first chip stack mounted on the substrate and having a plurality of first semiconductor chips stacked in a first direction in a stepped manner, each of the first semiconductor chips being provided with a first bonding pad at an end thereof on one side, a second chip stack mounted on the first chip stack and having a plurality of second semiconductor chips stacked in a second direction opposite to the first direction in a stepped manner.

Abstract: A method of manufacturing a high-capacity semiconductor package includes preparing a leadframe not comprising a chip mount area and comprising only a lead on a tape; attaching an interposer on a center area of the leadframe; stacking semiconductor chips stepwise on a first surface of the interposer; performing a first wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; performing a first molding process so as to encapsulate a top surface of the leadframe, the semiconductor chips, and wires; detaching a tape from the leadframe and turning the leadframe on which the first molding process has been performed upside down; stacking semiconductor chips on a second surface of the interposer; performing a second wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; and performing a second molding process so as to encapsulate a bottom surface of the leadframe, the semiconductor chips, and wires.

Abstract: A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.

Abstract: A printed circuit board for a semiconductor package which is capable of reducing noise by electromagnetic interference (EMI), including: an upper circuit layer in which a first circuit pattern is formed; an intermediate circuit layer that is disposed below the upper circuit layer and has a second circuit pattern formed therein; a lower circuit layer that is disposed below the intermediate circuit layer and has a third circuit pattern formed therein; an insulating layer disposed between the first and second circuit patterns and between the second and third circuit patterns; vias that vertically connect the first, second and third circuit patterns; and EMI blocking vias that are arranged along edge portions of the first, second and third circuit patterns and are connected to a ground layer.

Abstract: A method of manufacturing a semiconductor package having no chip pad includes preparing a polyimide tape on which an adhesive layer is arranged; forming lead members on the adhesive layer so as to form a plurality of semiconductor packages in a matrix form; attaching the polyimide tape to a carrier; performing wire bonding to mount semiconductor chips on the polyimide tape and connect the lead members and the semiconductor chips; forming an encapsulation member to encapsulate the semiconductor chips, the lead members, and wires; detaching the encapsulation member from the carrier and the polyimide tape; forming conductive layers each on a surface of the lead member exposed through a surface of the encapsulation member; and performing a singulation process on the encapsulation member with the conductive layers formed thereon to define unit semiconductor packages.

Abstract: A semiconductor package including: a lead frame including a chip attachment unit and a lead unit; a semiconductor chip that is mounted on the chip attachment unit of the lead frame; a wire that electrically connects the semiconductor chip to the lead unit; an insulation layer formed in the lead frame under the chip attachment unit; and an encapsulant that seals an upper portion of the lead frame, the semiconductor chip, and the wire, wherein the lead unit does not protrude to the outside of the encapsulant.