Abstract: An efficient streamlined cache coherent protocol for replacing data is provided in a multiprocessor distributed-memory computer system. In one implementation, the computer system includes a plurality of subsystems, each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. In one embodiment, when data is replaced from a requesting subsystem, an asynchronous flush operation is initiated. In this implementation, the flush operation includes a pair of decoupled local flush instruction and corresponding global flush instruction. By decoupling the local flush instructions from the global flush instructions, once the requesting processor in the requesting subsystem is done issuing the local flush instruction, the requesting processor does not have to wait for a corresponding response from home location associated with the data being replaced.

Abstract: A computer system has a CPU, a stack cache and a main memory. The main memory is a conventional untagged memory, where each memory location is a word having a bit size that is an integer power of 2 (e.g., 32, 64 or 128 bits per word). However, at least one stack cache associated with the CPU (and preferably integrated with the CPU on the same semiconductor circuit or in the same chip set) is a tagged memory where each data word of the stack cache has an associated tag. Whenever the stack cache overflows with data, at least a portion of the contents of the stack cache are stored in a previously established location in main memory so as to make room for storing additional data in the stack cache. In this stack cache swap out operation, the data values and tags in N evaluation stack entries of the evaluation stack cache are copied to the previously established main memory location.

Abstract: A method and apparatus for compiling source code that pre-evaluates certain semantic attributes during syntactical analysis. The invention performs certain type of semantic analysis, such as checking semantic attributes, during the operation of the syntactical analyzer, while the parse tree is being built, instead of waiting to perform these checks in a separate pass through the parse tree during semantic analysis. The present invention modifies the format of nodes in the parse tree to include fields for semantic attributes and modifies the actions associated with grammar productions so that they create parse tree nodes of the correct format. In addition, the present invention includes semantic attribute routines that determine the attribute values to store in the parse tree for the various semantic attributes.

Abstract: A plate formed with louvers and a depression to heat engage a hard disk drive motor is attached to such a drive. Heat from the motor is transferred to the plate. The louvers dissipate heat especially if they are in the path of a blower. The plate also protects the user from contact with drive components if touched during installation or removal of the drive while the drive is connected to a computer while electrically energized.

Abstract: A method and apparatus for representing and storing the schedules of recurring events. The schedules are represented by recurrence rules generated according to a specific grammar. According to the grammar, each recurrence rule is composed of one or more recurrence commands. Each recurrence command corresponds to a cycle and includes a time interval indicator that specifies the duration of the cycle and a repeat quantity that determines the number of times the cycle is repeated in the schedule. Each recurrence command may also include an occurrence list that specifies at what times during a particular cycle the event occurs. The occurrence list may specify times in absolute or relative terms. Thus, the grammar supports recurrence rules for representing the schedule "first and tenth of every month" as well as the schedule "second Thursday and last Friday of every month".

Abstract: The present invention provides a hybrid Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) caching architecture together with a cache-coherent protocol for a computer system having a plurality of sub-systems coupled to each other via a system interconnect. In one implementation, each sub-system includes at least one processor, a page-oriented COMA cache and a line-oriented hybrid NUMA/COMA cache. Such a hybrid system provides flexibility and efficiency in caching both large and small, and/or sparse and packed data structures. Each sub-system is able to independently store data in COMA mode or in NUMA mode. When caching in COMA mode, a sub-system allocates a page of memory space and then stores the data within the allocated page in its COMA cache. Depending on the implementation, while caching in COMA mode, the sub-system may also store the same data in its hybrid cache for faster access.

Abstract: A data processor supports the use of multiple memory models by computer programs. At a device external to a data processor, such as a memory controller, memory transactions requests are received from the data processor. Each memory transaction request has associated therewith a memory model selected from a predefined plurality of memory models. In a preferred embodiment, the predefined memory models supported are SSO (strong sequential order), TSO (total store order), PSO (partial store order) and RMO (relaxed memory order). Data representing pending memory transactions are stored in one or more pending transaction buffers and a pending transaction status array. The pending transaction status data includes memory transaction order data that indicates which of the pending memory transactions can be performed before other ones of the pending memory transactions.

Abstract: A test support tool system and method produce software test programs from a logical description of selected software. Test programs are created by producing a cause-effect graph from the logical description, creating a decision table, producing test cases, and synthesizing test cases into a test program. The test support tool system includes an interface for receiving a logical description of software, a logical database, an analysis and test case generation module, a control module, and a test program synthesis module.

Abstract: A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of separately processing a stream of non-multimedia instructions in addition to a stream of multimedia instructions such as are used in MPEG audio and video. The computer processor complex includes a visible register set including registers for a program counter and a data pointer. The program counter is used to hold the address in memory where the multimedia instructions are located and the data pointer indicates where the data, corresponding to these multimedia instructions, is located in memory. A hardware processor is coupled to a first bidirectional port on the visible register set and a multimedia coprocessor is coupled to a second bidirectional port on the visible register set. The bidirectional ports allow the hardware processor and the coprocessor to exchange data and status information typically using an interrupt based communication mechanism.

Abstract: A cache, storing misspelled or otherwise incorrect network addresses from a plurality of users and associated correct network addresses, is maintained at a proxy server or internet service provider. Addresses received from all users are checked against the cache to correct any misspellings or other situations in which the network address might be incorrect. The cache is periodically pruned of entries which aren't frequently used. The collective experience of a group of users can thus be utilized to correct a network address submitted by a user who has never visited a particular network address before.

Abstract: An efficient cache allocation scheme is provided for both uniprocessor and multiprocessor computer systems having at least one cache. In one embodiment, upon the detection of a cache miss, a determination of whether the cache miss is "avoidable" is made. In other words, would the present cache miss have occurred if the data had been cached previously and if the data had remained in the cache. One example of an avoidable cache miss in a multiprocessor system having a distributed memory architecture is an excess cache miss. An excess cache miss is either a capacity miss or a conflict miss. A capacity miss is caused by the insufficient size of the cache. A conflict miss is caused by insufficient depth in the associativity of the cache. The determination of the excess cache miss involves tracking read and write requests for data by the various processors and storing some record of the read/write request history in a table or linked list. Data is cached only after an avoidable cache miss has occurred.

Abstract: An applications programming interface 20 to a telecommunications management network includes a command language interpreter 24 and a compiler 40. A command string input/output format is provided, the command strings 42 including network management parameters. The interpreter includes interpreter scripts for converting the network management parameters between the command string format and a network management protocol compatible format. The compiler compiles interpreter scripts for encoding and decoding user defined parameter types, which are then loaded dynamically to the interpreter. The interface provides a convenient "command line" API, while at the same time permitting extensions to the interpreter in a dynamic manner.

Abstract: When monitoring a large number of information sources such as pages on the World Wide Web, a user may not have time to normally look at each source at regular intervals. A background process will connect to each source maintained in a database and calculate an estimate of how much the source has changed since the last time a user viewed it. The amount of change is graphically displayed to the user as part of an icon or file listing. The user can thus determine whether the amount of new material justifies connecting to the source.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: An architecture for an information appliance adapted for a specific application supports a variety of appliance personalities, relying on a single core technology. The information appliance comprises an application-optimized hardware platform, including a processor, a display coupled to the processor, an input/output device coupled to an information source and to the processor, a user input device, and working memory coupled to the processor. Non-volatile memory is coupled to the processor and stores appliance operating software and application software. The appliance operating software includes logic executed by the processor, which manages information flow from the information source through the working memory to the display, and the application software includes logic executed by the processor and responsive to the user input to manage selection of information from the information source.

Abstract: A combined file allocation table file system (CFAT file system) uses two or more FAT file systems with different cluster sizes to form a single user visible FAT file system to reduce disk fragmentation. The FAT file system having the largest cluster size is used to store all of the other small FAT file systems as files with holes. The clusters of the small FAT file systems thus do not occupy disk space until they are allocated. Files containing user data are stored in one or many of the large and small FAT file systems to achieve optimal storage. More clusters are available for storing files with sizes that are smaller than the size of one large cluster. A CFAT file system includes: a large file allocation table for large clusters, a file allocation table extension to provide holes within the CFAT file system, and any number of small file allocation tables providing a variety of small cluster sizes.

Abstract: A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise instructions from a number (m) threads. The instructions in each of the m threads are executed on one of the m strands using execution resources at least some of which are shared among the m strands. While the coded instructions comprise instructions from a number (n) threads, the processor is placed in a second configuration having a second number (n) of strands. The instruction are executed in each of the n strands using execution resources at least some of which are shared among the n strands.

Abstract: A process for generating method invocation instructions for a source-code program expressed in an object-oriented computer programming language is described. The process can be implemented as a compiler or, alternatively, as a combination of one or more utility routines and a compiler. The process first generates a global method selector list (hereinafter referred to as the dispatch table) comprising all of a target program's known method selector strings. Next, a unique constant value identifier is assigned to each unique method selector. Finally, as each source-code method call instruction is parsed during compilation, the compiler uses the method selector's identifier value to generate an instruction to directly load a unique constant value method identifier. In one embodiment, generation of the dispatch table is done a priori to the source-code program's compilation by a utility routine. In an alternative embodiment, the compiler performs these operations directly.

Abstract: An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1.DELTA.t. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) .DELTA.t. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized.