Abstract: Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.

Abstract: Provided is an insulated gate bipolar transistor power device. The IGBT power device includes a gate dielectric layer located above the two p-type body regions and the n-type drift region between the two p-type body regions, an n-type floating gate located above the gate dielectric layer; a gate located above the gate dielectric layer and the n-type floating gate; an insulating dielectric layer between the gate and the n-type floating gate; a first opening located in the gate dielectric layer, where the n-type floating gate is in contact with one of the two p-type body regions through the first opening to form a p-n junction diode; and a second opening located in the gate dielectric layer, where the n-type floating gate is in contact with the other of the two p-type body regions through the second opening to form the p-n junction diode.

Abstract: Provided is an IGBT device. The IGBT device includes an MOSFET cell array, where each MOSFET cell includes a p-type body region located at the top of an n-type drift region, an n-type emitter region located in the p-type body region, and a gate dielectric layer, a gate electrode and an n-type floating gate which are located above the p-type body region. The gate electrode is located above the gate dielectric layer, the n-type floating gate is located above the gate dielectric layer, and the gate electrode acts on the n-type floating gate through capacitive coupling. The n-type floating gate of at least one MOSFET cell is isolated from the p-type body region through the gate dielectric layer, and the n-type floating gate of at least one MOSFET cell contacts the p-type body region through an opening in the gate dielectric layer to form a p-n junction diode.

Abstract: Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.

Abstract: Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

Abstract: Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves.

Abstract: Provided is a trench-type power transistor. The trench-type power transistor includes a source, a drain, a first gate, a second gate, a body diode and a body region contact diode. The body diode and the body region contact diode are connected in series. The first gate controls turn-on and turn-off of a first current channel through a gate voltage, the second gate is connected to the source and controls turn-on and turn-off of a second current channel through a source voltage.

Abstract: Disclosed is a semiconductor power device, including a semiconductor substrate; a MOSFET region formed on the semiconductor substrate, where the MOSFET region includes at least one MOSFET unit; and at least one collector region located in the semiconductor substrate, where the collector region and the MOSFET unit form an insulated gate bipolar transistor.

Abstract: Disclosed is an insulated gate bipolar transistor (IGBT) power device, including a bipolar transistor, a first MOS transistor, a second MOS transistor, a body diode and a body region contact diode. An anode of the body region contact diode and an anode of the body diode are connected to the bipolar transistor. A first gate of the first MOS transistor is externally connected to a gate voltage of the IGBT power device and configured to control turning on and off of the first MOS transistor by means of the gate voltage of the IGBT power device. A second gate of the second MOS transistor is connected to an emitter voltage of the IGBT power device and configured to control turning on and off of the second MOS transistor by means of the emitter voltage of the IGBT power device.

Abstract: Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves.

Abstract: Provided are a super junction power transistor and a preparation method thereof. The super junction power transistor includes a first substrate epitaxial layer of a first doping type and a second substrate epitaxial layer of the first doping type disposed on the first substrate epitaxial layer, a drain region of the first doping type and multiple columnar epitaxial doping regions of the second doping type are formed in the first substrate epitaxial layer, and multiple trenches are disposed in the second substrate epitaxial layer, and a composite gate structures is formed in each of the multiple trenches, a body region of the second doping type is disposed in the second substrate epitaxial layer between adjacent trenches, and a source region of the first doping type is disposed in the body region.

Abstract: The present disclosure relates to the technical field of semiconductor power devices, and in particular relates to a semiconductor super-junction power device and a manufacturing method therefor. The super-junction power device of the present disclosure includes a termination region and a cell region; the cell region includes a substrate epitaxial layer and a drain region at a bottom of the substrate epitaxial layer, the substrate epitaxial layer has a plurality of pillar epitaxial doped regions and a plurality of JFET regions, a body region is arranged at a top of each of the plurality of pillar epitaxial doped regions; the body regions have at least two unequal widths; two source regions are arranged in each of the body regions; a gate oxide layer is arranged on the body regions and the JFET regions; and a gate is arranged on the gate oxide layer.

Abstract: The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge storage purpose, it can be electrically charged or discharged by current flowing through the gated p-n diode. An array of memory cells formed by the disclosed semiconductor memory device is proposed. Furthermore, an operating method and a method for producing the disclosed semiconductor memory device and array are described.