Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

Abstract: An extreme ultraviolet (EUV) photolithography system cleans debris from an EUV reticle. The system includes a cleaning electrode configured to be positioned adjacent the EUV reticle. The system includes a voltage source that helps draw debris from the EUV reticle toward the cleaning electrode by applying a voltage of alternating polarity to the cleaning electrode.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

Abstract: A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.

Abstract: A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist underlayer over a semiconductor substrate. The photoresist underlayer includes a polymer, including a main polymer chain having pendant target groups, and pendant organic groups or photoacid generator groups. The main polymer chain is a polystyrene, a polyhydroxystyrene, a polyacrylate, a polymethylacrylate, a polymethylmethacrylate, a polyacrylic acid, a polyvinyl ester, a polymaleic ester, a poly(methacrylonitrile), or a poly(methacrylamide). Pendant target groups are selected from the group consisting of a substituted or unsubstituted: C2-C30 diol group, C1-C30 aldehyde group, and C3-C30 ketone group. Pendant organic groups are C3-C30 aliphatic or aromatic groups having at least one photosensitive functional group, and pendant photoacid generator groups are C3-C50 substituted aliphatic or aromatic groups. A photoresist layer is formed over the photoresist underlayer.

Abstract: A semiconductor device includes a substrate, an active region, an isolation structure, a first metal line, gate structure, source/drain region, a source/drain contact, and a second metal line. The active region protrudes from a top surface of the substrate. The isolation structure is over the substrate and laterally surrounds the active region. The first metal line is in the isolation structure. The gate structure is over the active region. The source/drain region is in the active region. The source/drain contact is over the active region and is electrically connected to the source/drain region. The second metal line is over the gate structure and the source/drain contact, in which the second metal line vertically overlaps the first metal line.

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

Abstract: Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.