Patents Assigned to Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 11075151
    Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 11075087
    Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu Lun Ke
  • Patent number: 11075176
    Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hung-Yi Kuo, Hao-Yi Tsai, Ming Hung Tseng
  • Patent number: 11075133
    Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
  • Patent number: 11075173
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Patent number: 11075162
    Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
  • Patent number: 11075184
    Abstract: A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 11075145
    Abstract: A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a first semiconductor die, a second semiconductor die, a bonding layer, and a through die via. The first semiconductor die includes a first semiconductor substrate and a first conductive pad exposed at an active surface of the first semiconductor die. The second semiconductor die includes a second semiconductor substrate and a second conductive pad exposed at an active surface of the second semiconductor die. The first semiconductor die is stacked over the second semiconductor die. The bonding layer is disposed between the first and the second semiconductor die. The through die via electrically connects the first semiconductor die and the second semiconductor die. The through die via is embedded in the first semiconductor substrate, penetrates through the first conductive pad and the bonding layer, and reaches the second conductive pad.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 11075212
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip having a flash gate structure disposed over a substrate and including a control gate separated from a floating gate by an inter-electrode dielectric. One or more first sidewall spacers laterally surround the flash gate structure. The inter-electrode dielectric is directly between the one or more first sidewall spacers. A logic gate structure is disposed over the substrate and is laterally surrounded by one or more second sidewall spacers having a smaller height than the one or more first sidewall spacers.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Josh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho
  • Patent number: 11075168
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 11075201
    Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Guan-Lin Chen, Ting-Hung Hsu, Jiun-Jia Huang
  • Patent number: 11075238
    Abstract: A method of manufacturing an image sensor includes at least the following steps. A storage node is formed in a substrate. A gate dielectric layer, a storage gate electrode, and a first dielectric layer are sequentially formed over the substrate. A portion of the first dielectric layer is removed to form an opening. A protection layer and a shielding layer are sequentially filled into the opening. The protection layer laterally surrounds the shielding layer and at least a portion of the protection layer is located between the storage gate electrode and the shielding layer. A second dielectric layer is formed over the shielding layer.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hung Cheng, Kai-Fung Chang
  • Patent number: 11075267
    Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
  • Patent number: 11075278
    Abstract: A three-dimensional (3D) capacitor includes a semiconductor substrate; one or more fins extending from the semiconductor substrate; an insulator material between each of the one or more fins; a dielectric layer over a first portion of the one or more fins and over the insulator material; a first electrode over the dielectric layer; spacers on sidewalls of the first electrode; and a second electrode over a second portion of the one or more fins and over the insulator material, wherein the first and second portions are different.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 11075242
    Abstract: The present disclosure relates to a semiconductor device having a lateral resonance structure to coherently reflect light toward the image sensor. The semiconductor device includes an image sensing element arranged within a substrate. A radiation absorption region is arranged within the substrate and above the image sensor, and contains an array of protrusions having a characteristic dimension and an outer border. A resonant structure containing a plurality of deep trench isolation (DTI) structures is disposed on opposing sides of the image sensing element. The (DTI) structures surround the outer border of the array of protrusions. An inner surface of the DTI structure is laterally spaced apart from the outer border of the array of protrusions by a reflective length based on the characteristic dimension of the array of protrusions, thus affecting coherent reflection of light back toward the image sensor.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chia Kuo, Jhy-Jyi Sze, Tung-Ting Wu, Yimin Huang
  • Patent number: 11075279
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Teng Liao, Yi-Wei Chiu, Xi-Zong Chen, Chia-Ching Tsai
  • Publication number: 20210223708
    Abstract: Extreme ultraviolet (EUV) lithography systems are provided. A EUV scanner is configured to perform a lithography exposure process in response to EUV radiation. A light source is configured to provide the EUV radiation to the EUV scanner. A measuring device is configured to measure concentration of debris caused by unstable target droplets in the chamber. A controller is configured to adjust a first gas flow rate and a second gas flow rate in response to the measured concentration of the debris and a control signal from the EUV scanner. A exhaust device is configured to extract the debris out of the chamber according to the first gas flow rate. A gas supply device is configured to provide a gas into the chamber according to the second gas flow rate. The control signal indicates the lithography exposure process is completed.
    Type: Application
    Filed: March 18, 2021
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi YANG, Ssu-Yu CHEN, Shang-Chieh CHIEN, Chieh HSIEH, Tzung-Chi FU, Bo-Tsun LIU, Li-Jui CHEN, Po-Chung CHENG
  • Publication number: 20210225908
    Abstract: Image sensor structures are provided. The image sensor structure includes a substrate and a light-sensing region formed in the substrate. The image sensor structure further includes a first isolation structure surrounding the light sensing region and having an opening region in a top view and a second isolation structure formed in the substrate. In addition, the second isolation structure surrounds the light-sensing region and vertically overlaps both the opening region and the first isolation structure. The image sensor structure further includes a first gate structure formed over the substrate and overlapping the opening region, the first isolation structure, and the second isolation structure.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuichiro YAMASHITA, Chun-Hao CHUANG, Hirofumi SUMI
  • Publication number: 20210224193
    Abstract: An integrated circuit (IC) is provided. The IC includes a cache memory divided into a plurality of groups and an address decoder. The groups are assigned in rotation for a plurality of time periods. Each group is assigned in a corresponding single one of the time periods. The address decoder is configured to obtain a set address according to an access address and provide a physical address according to the set address. When the access address corresponds to a first group, the physical address is different from the set address. When the access address corresponds to the groups other than the first group, the physical address is the same as the set address. The sets of the first group that is assigned in a first time period are not overlapping with the sets of other first groups assigned in the time periods other than the first time period.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Lien Linus LU
  • Publication number: 20210225684
    Abstract: A workpiece holder includes a chuck body and a seal ring. The chuck body includes a receiving surface configured to receive a workpiece and at least one vacuum port configured to apply a vacuum seal. The seal ring surrounds a side surface of the chuck body. A top surface of the seal ring is higher than the receiving surface of the chuck body, and the workpiece leans against the seal ring when the vacuum seal is applied between the workpiece and the chuck body.
    Type: Application
    Filed: September 3, 2020
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Shiuan Wong, Chih-Chiang Tsao, Chao-Wei Chiu, Hao-Jan Pei, Wei-Yu Chen, Hsiu-Jen Lin, Ching-Hua Hsieh, Chia-Shen Cheng