Patents Assigned to Tamura Corporation
  • Publication number: 20210020789
    Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer stacked on the first semiconductor layer, includes a Ga2O3-based single crystal, and includes a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench electrode that is buried in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes an insulating dry-etching-damaged layer with a thickness of not more than 0.8 ?m in a region including the inner surface of the trench.
    Type: Application
    Filed: February 25, 2019
    Publication date: January 21, 2021
    Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc., TDK Corporation
    Inventors: Kohei SASAKI, Minoru FUJITA, Jun HIRABAYASHI, Jun ARIMA
  • Publication number: 20210001433
    Abstract: A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.
    Type: Application
    Filed: September 16, 2020
    Publication date: January 7, 2021
    Applicant: TAMURA CORPORATION
    Inventors: Yurika MUNEKAWA, Takeshi NAKANO, Masaya ARAI, Takanori SHIMAZAKI, Tsukasa KATSUYAMA
  • Patent number: 10861945
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 8, 2020
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Kohei Sasaki, Ken Goto, Masataka Higashiwaki, Man Hoi Wong, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Patent number: 10836000
    Abstract: A flux includes a rosin resin, an activator, a thixotropic agent, and a solvent. The solvent includes 30% by mass or more and 60% by mass or less monovalent alcohol with respect to a total mass amount of the flux. The monovalent alcohol has 18 or more and 24 or less of carbon atoms in one molecule.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 17, 2020
    Assignee: TAMURA CORPORATION
    Inventors: Masanori Shibasaki, Jun Sugimoto, Isao Sakamoto
  • Patent number: 10825935
    Abstract: A trench MOS-type Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench MOS gate that is embedded in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 3, 2020
    Assignees: TAMURA CORPORATION, National Institute of Information and Communications Technology
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Publication number: 20200296845
    Abstract: A gate driver includes: driver boards mountable on an IGBT module which is a driving-target external device; gate driver circuits which are formed on the driver boards and each apply a drive signal generated using power and a signal which are externally input through an input connector, to semiconductor elements of the IGBT module; and an insulating surrounding member disposed to surround a peripheral edge of the input-side driver board.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 17, 2020
    Applicant: TAMURA CORPORATION
    Inventors: Hirotoshi AOKI, Kiyotaka YOSHIDA, Tomohiko YOSHINO
  • Publication number: 20200243332
    Abstract: A semiconductor substrate that is used as an underlying substrate for epitaxial crystal growth carried out by the HVPE method includes a ?-Ga2O3-based single crystal, and a principal plane that is a plane parallel to a [100] axis of the ?-Ga2O3-based single crystal. An epitaxial wafer includes the semiconductor substrate, and an epitaxial layer including a ?-Ga2O3-based single crystal and formed on the principal plane of the semiconductor substrate by epitaxial crystal growth using the HVPE method. A method for producing an epitaxial wafer includes by using the HVPE method, epitaxially growing an epitaxial layer including a ?-Ga2O3-based single crystal on a semiconductor substrate that includes a ?-Ga2O3-based single crystal and has a principal plane parallel to a [100] axis of the ?-Ga2O3-based single crystal.
    Type: Application
    Filed: November 16, 2016
    Publication date: July 30, 2020
    Applicants: TAMURA CORPORATION, National University Corporation Tokyo University of Agriculture and Technology
    Inventors: Ken GOTO, Yoshinao KUMAGAI, Hisashi MURAKAMI
  • Publication number: 20200235234
    Abstract: A field-effect transistor includes an n-type semiconductor layer that includes a Ga2O3-based single crystal and a plurality of trenches opening on one surface, a gate electrode buried in each of the plurality of trenches, a source electrode connected to a mesa-shaped region between adjacent trenches in the n-type semiconductor layer, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on an opposite side to the source electrode.
    Type: Application
    Filed: September 26, 2018
    Publication date: July 23, 2020
    Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc.
    Inventor: Kohei SASAKI
  • Publication number: 20200200347
    Abstract: A light emitting device includes a laser diode that emits a blue light, and a wavelength conversion part that absorbs a part of light emitted from the laser diode and converts a wavelength thereof. The wavelength conversion part includes a YAG-based single crystal phosphor. Irradiance of light emitted from the laser diode and irradiated on the wavelength conversion part is not less than 80 W/mm2.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 25, 2020
    Applicants: TAMURA CORPORATION, KOHA CO., LTD.
    Inventors: Mikihiko UWANI, Akira ITO, Hiroyuki SAWANO, Kentaro TONE, Hiroaki SANO, Daisuke INOMATA, Kazuyuki IIZUKA
  • Patent number: 10676841
    Abstract: A semiconductor substrate for being used as a base substrate for epitaxial crystal growth by HVPE method includes a ?-Ga2O3-based single crystal, and a principal surface that is a plane parallel to a [010] axis of the ?-Ga2O3-based single crystal. An epitaxial wafer includes the semiconductor substrate, and an epitaxial layer that includes a ?-Ga2O3-based single crystal and is formed on the principal surface of the semiconductor substrate by epitaxial crystal growth using the HVPE method. A method for manufacturing the epitaxial wafer includes forming the epitaxial layer by epitaxial crystal growth using the HVPE method on the semiconductor substrate.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: June 9, 2020
    Assignees: TAMURA CORPORATION, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Ken Goto, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Publication number: 20200168460
    Abstract: A semiconductor substrate includes a single crystal Ga2O3-based substrate and a polycrystalline substrate that are bonded to each other. A thickness of the single crystal Ga2O3-based substrate is smaller than a thickness of the polycrystalline substrate, and a fracture toughness value of the polycrystalline substrate is higher than a fracture toughness value of the single crystal Ga2O3-based substrate.
    Type: Application
    Filed: July 9, 2018
    Publication date: May 28, 2020
    Applicants: TAMURA CORPORATION, SICOXS Corporation, National Institute of Information and Communications Technology
    Inventors: Akito KURAMATA, Shinya WATANABE, Kohei SASAKI, Kuniaki YAGI, Naoki HATTA, Masataka HIGASHIWAKI, Keita KONISHI
  • Publication number: 20200168711
    Abstract: A diode includes an n-type semiconductor layer including an n-type Ga2O3-based single crystal, and a p-type semiconductor layer including a p-type semiconductor in which a volume of an amorphous portion is higher than a volume of a crystalline portion. The n-type semiconductor layer and the p-type semiconductor layer form a pn junction.
    Type: Application
    Filed: July 23, 2018
    Publication date: May 28, 2020
    Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc.
    Inventor: Kohei SASAKI
  • Publication number: 20200144377
    Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 7, 2020
    Applicants: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Masataka HIGASHIWAKI, Yoshiaki NAKATA, Takafumi KAMIMURA, Man Hoi WONG, Kohei SASAKI, Daiki WAKIMOTO
  • Patent number: 10633761
    Abstract: Provided are a Ga2O3-based single crystal substrate including a Ga2O3-based single crystal which has a high resistance while preventing a lowering of crystal quality and a production method therefor. According to one embodiment of the present invention, the production method includes growing the Ga2O3-based single crystal while adding a Fe to a Ga2O3-based raw material, the Ga2O3-based single crystal (5) including the Fe at a concentration higher than that of a donor impurity mixed in the Ga2O3-based raw material, and cutting out the Ga2O3-based single crystal substrate from the Ga2O3-based single crystal (5).
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: April 28, 2020
    Assignee: TAMURA CORPORATION
    Inventor: Kohei Sasaki
  • Publication number: 20200102667
    Abstract: [Problem] To provide a crystal laminate structure having a ?-Ga2O3 based single crystal film in which a dopant is included throughout the crystal and the concentration of the dopant can be set across a broad range. [Solution] In one embodiment of the present invention, provided is a crystal laminate structure 1 which includes: a Ga2O3 based substrate 10; and a ?-Ga2O3 based single crystal film 12 formed by epitaxial crystal growth on a primary face 11 of the Ga2O3 based substrate 10 and including Cl and a dopant doped in parallel with the crystal growth at a concentration of 1×1013 to 5.0×1020 atoms/cm3.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicants: TAMURA CORPORATION, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Ken GOTO, Akinori KOUKITU, Yoshinao KUMAGAI, Hisashi MURAKAMI
  • Publication number: 20200101567
    Abstract: Molded solder includes first metal powder and second metal powder. The first metal powder has a first solidus temperature and a first liquidus temperature and includes an alloy containing metal elements. The second metal powder has a melting temperature or a second solidus temperature and a second liquidus temperature and includes single metal element or an alloy containing metal elements. The melting temperature and the second liquidus temperature are higher than the first liquidus temperature. The molded solder is so constructed that a mixture of the first metal powder and the second metal powder are press-molded. The molded solder is so constructed that a first solidus temperature of a solder becomes higher when the molded solder becomes the solder after the first metal powder has been melted by heating the molded solder at a temperature equal to or higher than the first liquidus temperature.
    Type: Application
    Filed: September 19, 2019
    Publication date: April 2, 2020
    Applicant: TAMURA CORPORATION
    Inventors: Isao SAKAMOTO, Akira KITAMURA, Hiroaki TANIGUCHI
  • Patent number: 10600874
    Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: March 24, 2020
    Assignee: TAMURA CORPORATION
    Inventors: Masaru Takizawa, Akito Kuramata
  • Publication number: 20200072875
    Abstract: A current sensor 100 includes: a magnetic core 104 which focuses a magnetic field generated by continuity of a current to be sensed IP; an element 108 which outputs a sensing signal according to an intensity of the magnetic field focused by the magnetic core 104; a circuit 116 which applies a feedback current to a winding 118 based on the sensing signal from the element 108 and balances magnetism; and a coupling circuit 124 which couples supply paths 123, 124 of a power supply 122 to the circuit 116 and an application path 117 of a feedback current to the winding 118 via capacitors C1, C2.
    Type: Application
    Filed: August 12, 2019
    Publication date: March 5, 2020
    Applicant: TAMURA CORPORATION
    Inventor: Kiyotaka MORITA
  • Patent number: 10580569
    Abstract: An electronic component 100 includes: a circuit board module 104 which is composed of a plurality of layers, and in which a primary circuit 120 and secondary circuits 122, 124 are each formed using wring patterns of a first layer L1 to an eighth layer L8; and a magnetic core 106 which magnetically couples the primary circuit 120 and the secondary circuits 122, 124. The circuit board module 104 includes: cutout portions 104b which are formed in a cutout shape from side edge portions toward an inner side and which position the magnetic core 106 at a predetermined attachment position in a state of housing the magnetic core 106; and widened portions 104c which continue from the cutout portions 104b and are formed in a cutout shape from the side edge portions toward the inner side of the circuit board module 104, and which are formed on sides of the magnetic core 106 so as to be larger than a width W1 for housing of the cutout portions 104b.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 3, 2020
    Assignee: TAMURA CORPORATION
    Inventors: Hiroo Ogawa, Tomohiko Yoshino
  • Patent number: D904991
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 15, 2020
    Assignee: TAMURA CORPORATION
    Inventors: Hirotoshi Aoki, Kiyotaka Yoshida, Tomohiko Yoshino