Patents Assigned to Texas Instruments Japan Ltd.
-
Publication number: 20090295973Abstract: This invention is a solid-state image pickup device that solves the problem of limited dynamic range in the high luminance region in an image sensor having white pixels. White pixels or yellow pixels and at least red pixels, green pixels or blue pixels are arranged in array form on the light receiving surface of a semiconductor substrate. White pixels or yellow pixels have an additional capacitance CS connected to the photodiode via the floating diffusion, a capacitance coupling transistor S that can couple or separate the floating diffusion and the additional capacitance. The proportion of white or yellow pixels to the total number of pixels is higher in a central portion of the light receiving surface than a peripheral portion. The white or yellow pixel may share a floating diffusion with a red, green or blue pixel.Type: ApplicationFiled: May 20, 2009Publication date: December 3, 2009Applicant: Texas Instruments Japan, Ltd.Inventors: Hiromich Oshikubo, Satoru Adachi, Koichi Mizobuchi
-
Patent number: 6007920Abstract: The wafer dicing/bonding sheet of the present invention comprises a soft film, a pressure sensitive adhesive layer formed on the soft film, a processing film for polyimide type resin composed of a heat resistant resin which has been formed on the pressure sensitive adhesive layer and a polyimide adhesive layer formed on the processing film. It is preferred that the processing film be a polyethylene naphthalate film whose surface has been subjected to an alkyd release treatment. The present invention facilitates expansion to be conducted after the wafer dicing.Type: GrantFiled: June 17, 1998Date of Patent: December 28, 1999Assignees: Texas Instruments Japan, Ltd., Lintec CorporationInventors: Norito Umehara, Masazumi Amagai, Mamoru Kobayashi, Kazuyoshi Ebe
-
Patent number: 5914859Abstract: An electronic component mounting base board comprises an insulating substrate provided with a mounting portion for mounting an electronic component and a heat-sink plate disposed on an lower surface of the insulating substrate, in which the insulating substrate is provided with a wiring pattern for signal or power, a grounding pattern and a grounding hole, and the grounding hole is provided on its inner wall with a metal plated film for electrically connecting to the grounding pattern and a solder is filled in an inside of the grounding hole for electrically connecting to the heat-sink plate.Type: GrantFiled: April 22, 1997Date of Patent: June 22, 1999Assignees: Ibiden Co., Ltd., Texas Instruments Japan, Ltd.Inventors: Masaru Takada, Kiyotaka Tsukada, Morio Nakao
-
Patent number: 5882956Abstract: A process for manufacturing a wafer dicing/bonding sheet of the present invention comprises a soft film, a pressure sensitive adhesive layer formed on the soft film, a processing film for polyimide type resin composed of a heat resistant resin which has been formed on the pressure sensitive adhesive layer and a polyimide adhesive layer formed on the processing film. It is preferred that the processing film be a polyethylene naphthalate film whose surface has been subjected to an alkyd release treatment. The present invention facilitates expansion to be conducted after the wafer dicing.Type: GrantFiled: January 21, 1997Date of Patent: March 16, 1999Assignees: Texas Instruments Japan Ltd., Lintec CorporationInventors: Norito Umehara, Masazumi Amagai, Mamoru Kobayashi, Kazuyoshi Ebe
-
Patent number: 5875124Abstract: A full adder that operates rapidly with low power supply voltage and minimal power consumption, and further, that occupies a small area on a semiconductor element. A sum signal calculation circuit 10 of full adder 1 performs addition of input signals A and B and carry in signal C and outputs sum signal S.sub.out. Carry signal calculation circuit 16 outputs carry out signal C.sub.out corresponding to the combination of the logic values of input signals A and B and carry in signal C. Sum signal calculation circuit (10) is composed of addition signal generation circuit (12) and sum signal generation circuit (14). Addition signal generation circuit 12 performs XOR logic operations on input signals A and B. Sum signal generation circuit 14 outputs the results of full addition operations on inputs signals A and B and carry in signal C as sum signal S.sub.out, based on the results of XOR logic operations by addition signal generation circuit (12) and carry in signal C.Type: GrantFiled: October 16, 1997Date of Patent: February 23, 1999Assignee: Texas Instruments Japan Ltd.Inventor: Hiroshi Takahashi
-
Patent number: 5650801Abstract: A drive circuit in which the rise and fall characteristics with multiple voltages are made the same, while maintaining a high breakdown voltage. Drive circuit 70, which supplies power supply voltages VH and VL and voltage VM intermediate between them to output pad 32, is composed of p-channel MOS transistor P5 and n-channel MOS transistors N5, N6 and N7. When the output voltage changes from VH to VM, both transistors N6 and N7 conduct, and when the output voltage changes from VL to VM, only transistor N6 conducts. The transistors that supply intermediate voltage VM are constructed of transistors of the same conductivity type, so that the rise and fall characteristics to VM can be made the same while the breakdown voltage of the transistors in the circuit that supplies this intermediate voltage VM is kept high.Type: GrantFiled: June 7, 1995Date of Patent: July 22, 1997Assignee: Texas Instruments Japan, Ltd.Inventor: Masahiko Higashi
-
Patent number: 5199071Abstract: A method and apparatus for matching operation modes of modems for connection of terminals to a telephone line, i.e., matching operation forms determined by a communication speed, a coding format, a synchronizing format, etc., on both the calling and answering sides of the telephone line. When the answering side detects an extension specifying signal sent from the calling side, an operation mode of a modem corresponding to the extension specifying signal is used to select the specified operation mode from among a plurality of operation modes for modem circuits equipped on the answering side, for matching the operation mode of the answering side modem with that on the calling side. The answering side modem has a function of detecting a push-button dial signal serving as the extension specifying signal, and a function of providing the plurality of operation modes for the modem and optionally changing the operation mode upon an instruction from an answering side terminal.Type: GrantFiled: July 10, 1990Date of Patent: March 30, 1993Assignees: NTT Data Communications Systems Corporation, Ohkura Electric Co., Ltd., Texas Instruments Japan Ltd.Inventors: Kenichi Abe, Masumi Kaneuchi, Kenji Kurashina, Kenzou Kaji, Kikuo Sumiyoshi
-
Patent number: 5153897Abstract: The operation modes of a plurality of modems in a communication system are matched with each other for connection of digital terminals to an analog telephone line on both the calling and answering sides of the analog telephone line. For example, operation modes of modems on both sides of the analog telephone line can automatically be matched with each other by transferring a mode instructing signal with DTMF, using multi-frequency DTMF symbols for a select signal employed in the telephone line, between digital terminals connected to both ends of the telephone line.Type: GrantFiled: July 10, 1990Date of Patent: October 6, 1992Assignees: Texas Instruments Japan Ltd., NTT Data Communications Systems Corporation, Ohkura Electric Co., Ltd.Inventors: Kikuo Sumiyoshi, Kenichi Abe, Masumi Kaneuchi, Kenji Kurashina, Kenzou Kaji