Patents Assigned to Texas Instruments
  • Monolithically integrated active snubber
    Patent number: 8796745
    Abstract: A semiconductor device containing an extended drain MOS transistor with an integrated snubber formed by forming a drain drift region of the MOS transistor, forming a snubber capacitor including a capacitor dielectric layer and capacitor plate over the extended drain, and forming a snubber resistor over a gate of the MOS transistor so that the resistor is connected in series between the capacitor plate and a source of the MOS transistor.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher Boguslaw Kocon
  • Low noise voltage regulator
    Patent number: 8797772
    Abstract: A low noise voltage regulator generally includes an output switching stage and an amplifier, both of which contribute current to produce an output voltage at a substantially constant level. The amplifier produces a current that is based on a difference between a reference voltage and a feedback of the output voltage. The current from the amplifier (and optionally also from a current ramp generator) counterbalances the current from the output switching stage to maintain the output voltage at the substantially constant level. The output switching stage is controlled in response to a level of the counterbalancing current.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Teddy D. Thomas, Gregory Stewart Waterfall
  • Four capacitor nonvolatile bit cell
    Patent number: 8797783
    Abstract: A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Dual-layer beam forming in cellular networks
    Patent number: 8797950
    Abstract: Single user and multiuser MIMO transmission in a cellular network may be performed by selecting by a base station (eNB) to transmit either one or two transmission layers. When one transmission layer is selected, a first transmission layer is precoded with a first precoder. A first demodulation reference signal (DMRS) sequence or a second DMRS sequence is selected by the eNB and precoded using the first precoder. The first transmission layer is transmitted with the selected precoded DMRS from the eNB to a user equipment (UE), and an indicator is transmitted to the UE to indicate which DMRS sequence is selected and transmitted.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Runhua Chen, Eko Nugroho Onggosanusi
  • Multiplexer coupled to second core output and first core input
    Patent number: 8799729
    Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • PMSM initial position detection system and method
    Patent number: 8796974
    Abstract: A system for determining an initial position of a rotor (9) of a PMSM motor includes a motor controller (2) coupled to a plurality of phase windings of the motor by means of an actuation circuit (3). A processor (12) and an interface circuit (14) are coupled to the processor and the phase windings. The processor determines if the rotor speed is zero, and if so causes the actuation circuit to sequentially apply voltage signals (Vab, Vba, Vac, Vca, Vbc, and Vcb) to the phase windings to produce corresponding phase winding current signals (Iab, Icb, Ica, Iba, Ibc, Iac) in the various phase windings. The phase winding current signals are sensed and digitized. The processor then determines a position of a magnetic flux path associated with the rotor by computing the initial position of the rotor from one of the digitized phase winding current signals associated with the predetermined magnetic flux path.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoyan Wang, Yateendra Deshpande
  • Pulse generation circuits in integrated circuits
    Patent number: 8797072
    Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Aatmesh Shrivastava, Rajesh Yadav
  • Configuration of rank indicator reporting instances
    Patent number: 8798023
    Abstract: A method for setting a periodicity and an offset in rank indicator (RI) reporting in a user equipment in a wireless communication system receives a radio resource control (RRC) signal from a base station, decodes a RI periodicity and offset configuration index, sets the periodicity and offset in accordance with said decoded periodicity and offset configuration index and reports a RI according to the set periodicity and offset. The periodicity is an integer and reporting a RI reports with equal the product of the periodicity and a period of reporting of the channel quality indicator (CQI) and the precoding matrix indicator (PMI).
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Runhua Chen, Tarik Muharemovic, Eko N Onggosanusi
  • Phase Locked Loop and Method for Operating the Same
    Publication number: 20140210529
    Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: Texas Instruments Deutschland GmbH
    Inventors: Puneet Sareen, Markus Dietl, Ketan Dewan, Edmond F. George
  • EDGE RATE CONTROL GATE DRIVE CIRCUIT AND SYSTEM FOR HIGH AND LOW SIDE DEVICES WITH LARGE DRIVER FET
    Publication number: 20140210533
    Abstract: An apparatus, comprising: a NFET current mirror having a first NFET and a second NFET; a PFET gate-coupled to the drain of the second NFET, wherein the PFET has a larger gain than the second NFET; a driver NFET having a gate that is coupled to the drain the PFET; wherein the second NFET is coupled through its source to the drain of the driver NFET.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Adam L. Shook
  • BI-DIRECTIONAL ESD PROTECTION CIRCUIT
    Publication number: 20140210053
    Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: ROBERT STEINHOFF, Jonathan Brodsky
  • Low-Complexity Sensor Displacement Tolerant Pulse Oximetry Based Heart Rate Measurement
    Publication number: 20140213863
    Abstract: Methods for heart rate measurement based on pulse oximetry are provided that can tolerate some degree of relative displacement of a photoplethysmograph (PPG) heart rate monitor device. In some methods, artifact compensation based on a reference signal is performed on the PPG signal data to remove artifacts in the signal that may be caused, for example, by changes in ambient light and/or motion of a person wearing the monitor device. The reference signal used for artifact compensation may be generated using an LED of a complementary wavelength to that of the LED used to generate the PPG signal, or by driving an LED at a lower current than the current applied to generate the PPG signal.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Vitali Loseu, Sourabh Ravindran
  • 1149.1 TAP LINKING MODULES
    Publication number: 20140215282
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • Capacitive Single Layer Multi-Touch Panel Having Improved Response Characteristics
    Publication number: 20140210765
    Abstract: An apparatus is provided. A substrate and a cover plate are provided. A sensor layer is formed on at least one of the substrate and the cover plate. The sensor layer includes a plurality of row electrodes and a plurality of column electrodes interleaved with the plurality of row electrodes, where each row electrode and each column electrode is formed of a plurality of stair-stepped diamonds. An insulator is also included so as to electrically isolate the plurality of row electrodes and the plurality of column electrodes, where the insulator is substantially transparent to visible spectrum light. The apparatus employs mirror symmetric row sensor routing placement. The routing placement provides reduction of row bonding pads by 50% to enhance manufacturing yield. Rearranging unit cells on the same layout results in a decrease of RC parasitics by 50%.
    Type: Application
    Filed: April 29, 2013
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Tao Peng
  • BI-DIRECTIONAL ESD PROTECTION CIRCUIT
    Publication number: 20140211347
    Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Robert Steinhoff, Jonathan Brodsky, Thomas A. Vrotsos
  • ADJUSTABLE DUMMY FILL
    Publication number: 20140215425
    Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Robert G. Fleck
  • CIRCUIT ASSEMBLY
    Publication number: 20140211439
    Abstract: A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.
    Type: Application
    Filed: May 23, 2013
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Mark Allen Gerber
  • Error Detection in Nonvolatile Logic Arrays Using Parity
    Publication number: 20140210511
    Abstract: A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Disk drive
    Patent number: 8791657
    Abstract: To provide a disk drive capable of inhibiting the occurrence of acoustic noise caused by a voltage pulse when the head is retracted using a speed control method using voltage obtained by rectifying a back electromotive force after the power source has been cut off from the rotation of a spindle motor. Retraction control circuit is used to control the on and off modes of transistors in accordance with the speed of VCM. The voltage across VCM becomes a voltage that can be regulated with VCM voltage control circuit. At this time, voltage is supplied to the terminals based on the voltage of ISO5V that is the rectified voltage of the back electromotive force of the spindle motor and the pulsating voltage is synchronized and produced at both terminals. As a result, the potential difference across VCM is such that the pulsating voltage is negated and acoustic noise is inhibited.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: July 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Masaki Yamashita, Chisako Asaoka, Nobuhiko Wasa
  • Computational lithography with feature upsizing
    Patent number: 8793626
    Abstract: A method of computational lithography includes providing through-focus critical dimension (CD) curves at a range of different focus values (Bossung curves) for a plurality of feature types that include different ratios of line width to space width. Using software run on a computing device, it is determined if there is at least one marginal feature type from the plurality of feature types based an image tool capability and a predetermined process specification affected by at least one of the plurality of feature types. Provided a marginal feature type is determined to be present, at least the marginal feature type(s) is upsized. A degree of upsizing increases as a curvature of the Bossung curves increases. A computational lithography model is compiled including the upsizing.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: July 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ashesh Parikh, Chi-Chien Ho, Thomas John Smelko