Abstract: A master electronic circuit (300) includes a storage (324) representing a wireless collision avoidance networking process (332) involving collision avoidance overhead and combined with a schedulable process (345) including a serial data transfer process and a scheduler, a wireless modem (350) operable to transmit and receive wireless signals for the networking process (332), and a processor (320) coupled with the storage (324) and with the wireless modem (350) and operable to execute the scheduler to establish and transmit a schedule (110) for plural serial data transfers involving the processor (320) and distinct station identifications, and to execute the serial data transfers inside the wireless networking process and according to the schedule so as to avoid at least some of the collision avoidance overhead. Other electronic circuits, processes of making and using, and systems are disclosed.

Abstract: An electronic device includes a circuit for measuring a current in an inductor, wherein the current in the inductor is controlled by alternately switching a first power transistor and a second power transistor each having a first electrode, a second electrode and a control gate. The measuring circuit includes a first sense transistor having a first electrode, a second electrode and a control gate, the first sense transistor having the control gate coupled to the control gate of the first power transistor. A second electrode is coupled to the second electrode of the first power transistor. A second sense transistor has a first electrode, a second electrode and a control gate, the second sense transistor having the control gate coupled to the control gate of the second power transistor and having the second electrode coupled to the second electrode of the second power transistor.

Abstract: Scanning mirror based display system and method. A method comprises sampling a scanned light provided by a scanning mirror, converting the sampled scanned light into an electrical signal, analyzing the electrical signal to determine a position of the scanned light, and controlling the light source or the scanning mirror based on the analyzed electrical signal. The electrical signal based on the sampled scanned light may be used to ensure proper operation of the scanning mirror display system, such as determining failure of the scanning mirror, proper rendering of colors, determining whether the scanned light is following a desired scan path at a desired scan rate, and so forth.

Abstract: An integrated circuit containing a configurable dual n/p-channel 3-D resurf high voltage MOS field effect transistor (MOSFET) is disclosed. An n-channel drain is coterminous with a p-channel source in an n-well, and a p-channel drain is coterminous with an n-channel source in a p-well. A lateral drift region including n-type drift lanes and p-type drift lanes extends between the n and p wells. A resurf layer abuts the lateral drift region. The n-channel MOS gate is separate from the p-channel MOS gate. The p-channel MOS gate may be operated as a field plate in the n-channel mode, and vice versa. An n-channel MOS transistor may be integrated into the n-channel MOS source to provide an n-channel cascode transistor configuration, and similarly for a p-channel cascode configuration, to debias parasitic bipolar transistors under the MOS gates. Circuits using the MOSFET with various loads are also disclosed.

Abstract: Conventional circuits often have undesirable characteristics to due “hot spots” or use a large amount of area. Here, however, a charging circuit is provides that uses an improved driver. Namely, an amplifier within a current sensor is used to control the rate that a switch can charge an external capacitor. This is accomplished through the adjustment of the gain of the amplifier during a charging mode.

Abstract: System and method for adjusting the color segment durations for colors in a color sequence in sequential color display systems. A preferred embodiment comprises receiving a desired color sequence to display, computing a scaling factor for each color in the desired color sequence based on a reference color sequence, and sequentially displaying the colors in the desired color sequence. The reference color sequence used in computing the scaling factors specifies a duration for each color in the reference color sequence, while the desired color sequence specifies a desired duration for each color in the desired color sequence. The use of a single reference color sequence to create a large number of color sequences can save a significant amount of storage space and can allow for the storage of reference color sequences to meet varying chromatic properties due to changes in the display system, user settings, and operating environment.

Abstract: A quiet motor control system is described. This system digitally determines modulated voltages applied to motor phases in a manner that compensates for winding torque distortions, which reduces acoustic emissions.

Abstract: In versions 1.1a and 1.2 of the DISPLAYPORT™ standard, capacitors are used between a sourcing circuit and a switch for the auxiliary channel. As a result, these capacitors are generally uncharged when the switch activates the auxiliary channel, which can result in errors. Here, a switch is employed that uses precharge circuits to precharge these capacitors. Thus, errors due to charging of these capacitors can be reduced.

Abstract: A method for digitizing at least a portion of a selected analog input signal of a plurality of analog input signals by using a multiplexer having a plurality of channels is provided. Each channel for the multiplexer is associated with at least one of the analog input signals and is associated with a pair of select signals, and wherein each channel includes a cell having an input terminal, an output terminal, and a boosted NMOS switch. According to the method, a first select signal from each pair of select signals is asserted to decouple the input and output terminals for each cell. A boost capacitor is also charged during the non-sampling or conversion phase while the first select signal from each pair of select signals is asserted.

Abstract: A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.

Abstract: A method is provided of coordinating adjacent first and second wireless networks, comprising: receiving a signal at a controller on a wireless device, the received signal indicating an intended transmission state of the first network during a future time slot, the intended transmission state indicating whether or not the first network intends to transmit first data during the future time slot; transmitting second data in the second network to a remote device if the intended transmission state indicates that the first network does not intend to transmit first data during the future time slot; and controlling transmission of the second data in the second network such that the transmission ends during the future time slot in which the first network does not intend to transmit first data, with sufficient time remaining to allow the second network to receive a reply transmission from the remote device.

Abstract: A method includes transporting audio/video data using at least one signal line in a cable. The method also includes concurrently transporting at least about 100 W of power for operating an audio/video device using at least one electrical conductor in the cable, the audio/video device coupled to the cable. The cable could include multiple electrical conductors, and the at least one signal line in the cable could include one or more of the electrical conductors in the cable. The data and the power can be transported using at least one common electrical conductor in the cable. The audio/video data could have a data rate of at least about 7 Gbps, and the power could be at least about 200 W of power.

Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

Abstract: In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN) operations in a limited multipath environment based on a constant symbol rate for BAN packet transmissions and based on M-ary PSK, differential M-ary PSK or rotated differential M-ary PSK modulation. The PHY layer is configured to transmit and receive data in a frequency band selected from the group consisting of: 402-405 MHz, 420-450 MHz, 863-870 MHz, 902-928 MHz, 950-956 MHz, 2360-2400 MHz, and 2400-2483.5 MHz.

Abstract: A wireless data platform comprises a plurality of processors. Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler executed on one processor compiles code into native processing code for another processor. A dynamic cross linker links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.

Abstract: An output stage of a switching DC-DC converter includes a pair of transistors and a bias transistor connected between the transistors. A voltage regulator generates a bias voltage to bias a control terminal of the bias transistor with a fixed bias voltage. The voltage regulator is operable in a full-power mode and a low-power mode. The voltage regulator consumes larger current in the full-power mode than in the low-power mode. At low load currents, the voltage regulator is operated in the low-power mode when both the transistors in the pair of transistors are off, and in the full-power mode otherwise.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: A storage Pod for semiconductor substrates includes a top cover formed from a non-air permeable (NAP) material having faces including a top and a plurality of sides. A bottom base plate has a locking structure configured for providing a locking position for locking the sides, and for providing an unlocked position where the sides are detached from the bottom base plate. The top cover includes at least one aperture in the NAP material for allowing surrounding gases in an environment around the storage Pod to flow into the storage Pod to permit a gas sensor within the storage Pod to sense the target gas.

Abstract: An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal, wherein if the clock for the charge pump is running faster than an analog front end (“AFE”) video sampling clock, a state-machine control is configured to: skip the charge pump clock period right before a video sample signal falling edge, thereby recovering to a normal operation the next charge-pump clock period, wherein this duty cycle modulation of charge pump clock will not substantially impact charge pump output.

Abstract: An electronic circuit comprising a transistor-based RF (radio frequency) power amplifier (112) having balanced outputs (172, 176), a transistor-based receiver RF amplifier (116) having balanced inputs (152, 156) ohmically connected to said balanced outputs (172, 176) respectively of said RF power amplifier (112), and a balun (114) having a primary (182, 186) and a secondary (188), said primary (182, 186) having primary connections and a supply connection (185) of said primary (182, 186) intermediate said primary connections and said primary connections ohmically connected both to said balanced outputs (172, 176) of said RF power amplifier (112) respectively and to said balanced inputs (152, 156) of said receiver RF amplifier, thereby to switchlessly couple RF between the balun (114) and the RF power amplifier (112) and switchlessly couple RF between the balun (114) and the receiver RF amplifier (116). Other electronic circuits, processes, devices and systems are disclosed.