Abstract: A method of packing electronic devices and an apparatus thereof are disclosed herein. The method allows for usage of solder materials with a melting temperature of 180° C. or higher, such as from 210° C. to 300° C., and from 230° C. to 260° C., so as to provide reliable and robust packaging. This method is particularly useful for packaging electronic devices that are sensitive to temperatures, such as microstructures, which can be microelectromechanical devices (MEMS), such as micromirror array devices.

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (106). The copper (110) is then deposited over the transition metal-silicon-nitride barrier (108) with good adhesion.

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract: A method and apparatus for white balancing. The method comprising estimating the color temperature of at least a portion of the image, wherein the color temperature estimation algorithm is based on computing histogram correlations of at least a portion of at least one reference image and at least a portion of at least one target image, and correcting the white balance of at least a portion of the image utilizing the estimated color temperature.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage.

Abstract: The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

Abstract: A disk drive controller including a differential voice coil motor control function is disclosed. The differential voice coil motor control function includes an on-chip compensation network for the inner control loop, including a resistor formed of one or more MOS transistors connected in series. The gate of the MOS transistors in the compensation network is driven with a bias voltage based on a tuning current, where the tuning current is derived so that it varies with process and temperature variations of the integrated circuit, for example with variations in an on-chip capacitor. The on-chip compensation network can be tuned with sufficient precision to properly compensate the inner control loop to provide the desired frequency response in driving the voice coil motor in the disk drive.

Abstract: A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a data output providing a digital data output signal (Qn) for application to a data destination device such as memory devices. The buffer further has a clock output for providing an output clock signal (QCLK) to the data destination device and a phase-locked loop (PLL) with a clock input, a feedback input, a feedback output and a plurality of clock outputs. The buffer uses a pair of data registers, i.e. flip-flops (FF1, FF2) connected in series in each data path. The first data register in each data path is clocked by the clock input signal (CLK) and the second data register in each data path is clocked by one of the clock outputs (PDCLK) from the PLL.

Abstract: A file archive system for storing multiple files and directories as a single file. The file archive system could be used on a hand-held computer or other computing device. The file archive system in a preferred embodiment has an operating system with a loadable file system. In another embodiment, the file archive system includes a file archive structure for storing multiple files as a single file.

Abstract: Color filter array demosaicing as is useful in digital cameras, still and video, using a single sensor includes blending of directional and non-directional interpolations. Directional interpolation uses edge detection with lowpass filtering with neighboring pixels for erroneous detection correction.

Abstract: A method and apparatus for a projection display system includes a spatial light modulator and a volume illumination hologram. The spatial light modulator comprises a digital micromirror device, and the projection system includes a laser light source to produce a sequence of collimated, colored, light beams for the illumination hologram. Waste light produced by the spatial light modulator is transmitted to the illumination hologram, and the illumination hologram emits waste light from at least one of its edges. Waste light emitted from an edge of the illumination hologram is absorbed by a light sensor to control the intensity of the light beams. A projection focusing element is mounted proximate a side of the illumination hologram to focus the image beam from the spatial light modulator for viewing. A projection hologram is interposed between the side of the illumination hologram and the projection focusing element to manage waste light.

Abstract: A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the network interface. The at least one integrated circuit assembly provides media over packet transmissions and holds bits defining reconstruction of a packet stream having a primary stage and a secondary stage. The secondary stage has one or more of linear predictive coding parameters, long term prediction lags, parity check, and adaptive and fixed codebook gains. The packet stream has an instance of single packet loss, and the reconstruction includes receiving a packet sequence represented by P(n)P(n?1)?, [Lost Packet], P(n+2)P(n+1)?, and P(n+3)P(n+2)?, obtaining as information from the secondary stage one or more of the linear predictive coding parameters, long term prediction lags, parity check, and adaptive and fixed codebook gains, and performing an excitation reconstruction utilizing said packet sequence thus received.

Abstract: A DC-DC converter operates outside of an audible frequency range under light current load conditions with reduced switching frequency by reducing supply current and regulating output voltage. A control for the converter maintains the switching frequency above an audible frequency range and reduces supply current by modulating switch on-time, sinking supply current, or permitting negative supply current values. The output voltage of the converter is regulated by modulating switch on-time, clamping output voltage, or modifying feedback detector thresholds. The power converter operates with improved efficiency under light current load conditions, while avoiding operation in an audible frequency range to prevent the generation of audible noise in converter components.

Abstract: A method of fabricating a micromechanical device. Several of the micromechanical devices are fabricated 20 on a common wafer. After the devices are fabricated, the sacrificial layers are removed 22 leaving open spaces where the sacrificial layers once were. These open spaces allow for movement of the components of the micromechanical device. The devices optionally are passivated 24, which may include the application of a lubricant. After the devices have been passivated, they are tested 26 in wafer form. After testing 26, any surface treatments that are not compatible with the remainder of the processing steps are removed 28. The substrate wafer containing the completed devices receives a conformal overcoat 30. The overcoat layer is thick enough to project the micromechanical structures, but thin and light enough to prevent deforming the underlying micromechanical structures.

Abstract: The present application describes a system and method for determining characteristics (e.g., exact band location, orientation and height and the spot shape and size of a single wavelength and the like) of an optical signal projected on a spatial light modulator. In an embodiment, images with sharper edges (i.e. clear boundary between ‘on’ pixels and ‘off’ pixels) on the spatial light modulator are used to obtain spectral information from a referenced broadband source. The spectral information can be used to determine the desired characteristics of optical signals projected on the spatial light modulator.