Abstract: An electronic device includes a low drop-out regulator for providing a regulated output voltage. The low drop-out regulator generally comprises a power MOSFET transistor having a gate coupled to a driver. The driver has a first path including an NMOS transistor and being coupled to the gate of the power MOSFET, a second path having a PMOS transistor and being coupled to the gate of the power MOSFET, and a switch for alternately switching between the first and second paths so as to provide a voltage to the gate of the power MOSFET ranging from ground to a power supply level.

Abstract: Attaching a semiconductor chip to a substrate by applying mechanical vibrations (150) to a polymeric compound (130) and the contacting areas (114, 124) of a first (113) and a second (121) metallic member immersed in the compound, while the two metallic members approach (140) each other until they touch. The mechanical vibration causes displacements of the first member relative to the second member, and the vibration includes displacements (150) oriented at right angles to the direction (140) of the approach. The polymeric compound (130) includes a non-conductive adhesive resin paste (NCP) and filler particles; the paste is deposited before the attaching step. The first member (113) is affixed to the chip and the second member (121) to the substrate.

Abstract: A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.

Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.

Abstract: Various cryptographic locks for securing assets, secure containers and methods of operating a cryptographic lock. One embodiment of a cryptographic lock includes: (1) a shape memory alloy (SMA) having a first and second phase, wherein the first phase inhibits access to an asset and the second phase allows access to the asset and (2) an RFID transponder, coupled to the SMA, configured to receive an authentication signal from an RFID transceiver and, based thereon, energize the SMA to temporarily change the SMA from the first phase to the second phase.

Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.

Abstract: A linear voltage regulator is provided which has a pair of complementary power transistors connected “back to back” in series between a voltage input and a voltage output. A current sense circuit is connected in parallel across one of the power transistors, such as the one connected to the voltage input. The current sense circuit includes a current sense resistor. A reference current path has a reference resistor connected in series with a current sink between the voltage input and a reference terminal, usually ground. A comparator has a first input connected to a terminal of the current sense resistor and a second input connected to a node between the reference resistor and the current sink. The comparator compares the voltage drop across the current sense resistor with the constant voltage drop across the reference resistor and provides an output signal indicative of an open load condition when the voltage drop across the current sensor falls below that of across the reference resistor.

Abstract: In one aspect, an integrated circuit device including a first-level module configurable to receive and transmit control information, said first level module including a first sub-level module, a second sub-level module operably coupleable to the first sub-level module, and a third sub-level module operably coupleable to the second module; and a second-level module operably coupleable to the first-level module is disclosed.

Abstract: A system and method for amplifier gain measurement and compensation. A method for compensating a signal gain of an amplifier circuit includes determining a desired gain for the amplifier circuit, determining an operating temperature of the amplifier circuit, adjusting a set of signal gains based on the operating temperature to produce a set of adjusted signal gains, determining a desired gain setting based on the desired gain and the set of signal gains, and providing the desired gain setting to the amplifier circuit.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.

Abstract: A semiconductor device comprises a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprises a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.

Abstract: Methods and apparatus to perform hard-disk drive head proximity detection in a preamplifier are described. One example method of detecting head position in a hard-disk drive includes obtaining a read signal from a head reading information from a disk; determining a signal envelope of the read signal; comparing the signal envelope to a first threshold to produce a first comparison; filtering the signal envelope; comparing the filtered signal envelope to a second threshold to produce a second comparison; combining the first comparison and the second comparison; and determining if the combination of the first comparison and the second comparison indicates head position oscillation.

Abstract: A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

Abstract: A method and/or a system of at-speed transition fault testing with low speed scan enable is disclosed. In one embodiment, a digital system includes any number of scan chains. Each scan chain may have any number of scan cells, an at-speed local scan enable signal to control a mode of operation, and any number of last transition generator cells. In addition, each last transition generator cell includes a first flip-flop with an output connected to a second flip-flop input, an input multiplexer to apply any one of a first flip-flop output data and an OR gate having a first flip-flop input based on a state of the at-speed local scan enable signal, and an OR gate having a first flip-flop output and the global scan enable signal as inputs to generate the at-speed local scan enable signal based on a state of the global scan enable signal.

Abstract: An apparatus for reducing current leakage between an input locus and at least one power rail for a system includes, for each respective power rail: (a) A first diode unit coupled between the input locus and a coupling locus. The first diode unit is configured to effect substantially zero potential drop during normal operation of the apparatus. (b) A second diode unit coupled between the coupling locus and the respective power rail. The second diode unit is configured to present no forward bias during normal operation of the apparatus. The first and second diode units cooperate to effect current flow between the input locus and the respective power rail during a predetermined operational condition of the apparatus.

Abstract: A system and method for providing a fuel dispenser with radio frequency customer identification capabilities. The system and method determines whether a transponder containing customer identification data is within range of a dispenser, the dispenser requiring activation by the customer to initiate a transaction and including a reader associated therewith for emitting radio frequency signals within the dispenser range, and for receiving customer identification data from the transponder responsive to the emitted radio frequency signals received by the transponder. When the transponder is within range of the dispenser, an in-range indication is provided to the customer. A determination is made whether the dispenser has been activated by the customer following a determination that the transponder is within the dispenser range.

Abstract: Various systems and methods for pulse width modulated clocking in a temperature measurement are disclosed. For example, some embodiments of the present invention provide temperature measurement systems with a variable current source, a transistor, and a pulse width modulation circuit. The variable current source is operable to provide a first current and a second current that are applied to the transistor. A first base-emitter voltage occurs on the transistor when the first current is applied, and a second base-emitter voltage occurs on the transistor when the second current is applied. The first base emitter voltage is associated with a first sample period, and a second base-emitter voltage is associated with a second sample period. The pulse width modulation circuit provides a pulse width modulated clock including a combination of the aforementioned first period and second period.

Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.

Abstract: In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.