Abstract: An overflow problem of LSF quantization in G.729 Annex B speech encoding which may lead to non-assignment of a codebook index. Preferred embodiments fix the problem with default or limited random variable assignments or flagging the overflow and adjusting the frame encoding such as by limiting spectral components or changing quantization targets.

Abstract: A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the first and second regions. A mask is then formed that exposes the second region and covers the first region. A material is selected for a modification implant and the selected material is implanted into the second region thereby converting a portion of the modifiable tensile strain inducing layer into a compressive strain inducing layer within the PMOS region.

Abstract: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

Abstract: According to one embodiment of the invention, a method for enhancing multiple feature lithography is provided. The method includes generating a plurality of maps each associated with a particular one of a plurality of circuit features. Each map maps an illumination field comprising a plurality of point sources and indicates, in terms of a process metric and for each point source, a level of feature quality that will result from using the each point source to image the each circuit feature. The method also includes identifying, based on the maps, a group of one or more of the point sources that, if used to image the circuit features onto a target surface, will result in an overall feature quality level equal to or greater than a predetermined quality threshold.

Abstract: A wireless receiver (301) for receiving multiple space time encoded signals from a plurality of transmit antenna sets (TAT1 through TAT2, and TAT3 through TAT4), wherein the multiple space time encoded signals comprise a set of symbols and wherein each transmit antenna set is coupled to a corresponding encoder (221, 222) at a single transmitter (121). The receiver comprises a plurality of receive antennas (RAT1 through RATQ) and collection circuitry (32), coupled to the plurality of receive antennas, for collecting a plurality of signal samples for a plurality of successive time instances and from each of the plurality of receive antennas. The collected samples comprise samples of multipaths of the space time encoded signals. The receiver also comprises circuitry (34, 36), coupled to the plurality of receive antennas, for determining a linear time invariant multiple-input multiple-output matrix in response to pilot values in the received multiple space time encoded signals.

Abstract: A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.

Abstract: System and method for improving the detection performance of a wirelessly transmitted signal. A preferred embodiment comprises specifying a desired response for missed channel detection and false alarm probabilities for a plurality of signal qualities and determining if a channel detection threshold is based on missed channel detection or false alarm probabilities for the plurality of signal qualities. A signal quality estimate of a channel can be inferred from a signal quality measurement of a second channel, wherein the channel and the second channel are sourced by a single transmitter. The channel detection threshold can be adjusted based upon the previously determined required response and the signal quality estimate of the channel.

Abstract: A system and method for the modulation of light propagating along an optical path, for example the optical path in a projection display system. As light in the optical path travels from a light source to a display screen, it is shaped and modulated by the various components of the optical path so that the intended visual image appears on the display screen. In accordance with the present invention, a mirror disposed proximate the optical path is operable to be selectively inserted and removed from the optical path to alternately direct the light from one portion of the optical path to another, or to a light dump where it can be absorbed such that the associated heat energy may be properly dissipated. In a preferred embodiment, the mirror is a fold mirror mounted at a stop of the system to fold the light beam approximately 90 degrees when the mirror is inserted in the optical path.

Abstract: A static random-access memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) a row of SRAM cells coupled to a word line and a power source configured to vary in voltage to enable the row of SRAM cells to operate in a retain-till-accessed (RTA) mode and (2) a word line driver coupled to the power source and configured to drive the word line.

Abstract: Hybrid linear predictive speech coding system with phase alignment predictive quantization zero phase alignment of speech prior to waveform coding aligns synthesized speech frames of a waveform coder with frames synthesized with a parametric coder. Inter-frame interpolation of LP coefficients suppresses artifacts in resultant synthesized speech frames.

Abstract: A first-order signal generator (135). The generator comprises a shift register (210?) having a number N of bit positions. Each bit position is operable to store a binary value, the shift register operable to shift the binary value at each of the bit positions. The generator also comprises circuitry for tapping selected ones of the bit positions and circuitry for applying a function (220?) to each binary value in the selected ones of the bit positions to provide a function output. The generator also comprises circuitry for coupling the function output as an input to one of the bit positions. Lastly, the generator also comprises circuitry (230?) for outputting a first-order noise signal by coupling, as a twos complement number, each binary value in a plurality of the bit positions.

Abstract: An apparatus for and method of extending the dynamic range of a RF communications receiver. The invention provides a mechanism for controlling the gain of both the LNA and down conversion mixer in the front end portion of an RF receiver. Both the LNA and the mixer are adapted to have both low and high gain modes of operation. The control mechanism typically comprises a two bit gain control that places both the LNA and mixer in one of four operating gain mode states. The selection of the most appropriate operating gain mode state, is preferably determined in accordance with various metrics such as the received levels of the desired signal, levels of interference signals, bit error rate and receiver RSSI.

Abstract: An all-digital phase locked loop system for generating an oscillator output signal under control of a digital reference input. The system comprises a digitally controlled oscillator, a digital loop filter for generating a multiple bit digital control signal for the digitally controlled oscillator, a sigma-delta modulator for generating an additional 1-bit digital control signal for the digitally controlled oscillator, a digital divider dividing the oscillator output signal and providing a digital divided signal, and a digital adder with a first, additive input to which the digital reference input is applied and a second, subtractive input to which the digital divided signal is applied. The digital adder provides a digital output, the most significant bits of which are applied to an input of the digital loop filter and the least significant bits of which are applied to an input of the sigma-delta modulator. In the preferred embodiment, the sigma-delta modulator is of a two-stage MASH configuration.

Abstract: A bootstrapped circuit for sampling inputs with a signal range greater than supply voltage includes: a bootstrapped switch coupled between an input node and an output node; a first transistor coupled to a control node of the bootstrapped switch; a first capacitor having a first end coupled to the first transistor; a second transistor coupled between the first transistor and a supply node, and having a control node coupled to a first clock signal node; a third transistor coupled between the first transistor and the supply node; a charge pump having an output coupled to a control node of the third transistor; a level shifter coupled to a second end of the first capacitor; a fourth transistor coupled between the supply node and a control node of the first transistor; and a fifth transistor coupled between the control node of the fourth transistor and the output of the charge pump and, having a control node coupled to the supply node; wherein the second end of the first capacitor can be charged to an input voltag

Abstract: A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement structures provided either on-chip or within the scribe lines. A set of memory structures may comprise first and second test structures, individually comprising a memory cell, having one or more left and right half-bit test structures having hard-wired connections between select nodes of each memory cell half-bit and one or more voltage supplies. The half-bits of the first test structure are configured for measuring respective left and right standby SNM values, and the half-bits of the second test structure are configured for measuring respective left and right cell ratio values at respective output nodes of the structures, using applied supply voltages for on-chip assessment of the static noise margin of the memory cells.

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.

Abstract: An SRAM memory cell structure utilizing a read driver transistor and a column select write transistor, and a method of operating the same. The SRAM memory cell comprises first and second cross-coupled inverters, having a first and second latch nodes, respectively. The cell further comprises a first write pass transistor connected between the first latch node of the first inverter and a first pass node, and a first wordline pass transistor connected between the first pass node and a first bitline. The cell also includes a first read driver connected between the first pass node and a source potential, and a control terminal of the first read driver connected to the second latch node of the second inverter.

Abstract: A programmable co-processor system comprising a datapath, a microprogram, and a microcontroller is provided. The datapath includes one or more datapath elements operable to receive input signals. The microprogram memory includes a microprogram operable to control the datapath in order to process the input signals. The microcontroller is operable to modify the microprogram based on a modification command.

Abstract: The invention provides, in one aspect, a method of forming a semiconductor device including providing a semiconductor substrate that comprises a first portion having a crystal orientation and a second portion located over the first portion and having a different crystal orientation. An interfacial region is located between the first portion and second portion. A passivating dopant is implanted into the interfacial region to passivate unterminated bonds within the interfacial region.