Abstract: A method for cleaning a semiconductor device has the steps of securing a wafer (16) with a modified chuck (11) and applying a cleaning solution (18) to the backside (20) of the wafer (16). The cleaning solution (18) is formulated to remove PTFE from the wafer (16). The cleaning solution (18) is applied to the edge (14) of the wafer (16) because of the characteristics of the modified chuck (11) to remove PTFE impurities that gather on the edge (14) of the wafer (16).

Abstract: An analog Ethernet detector determines if an IEEE 1394b long haul application using Category 5 (CAT 5 UTP) cable, is connected to an Ethernet which share certain pins of the RJ45 connector used to connect devices to the CAT 5 cable. The detector does not require a processor core or clocking and can be built as a completely analog device.

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Abstract: Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.

Abstract: In some embodiments, a system comprises a processor that executes an algorithm. Coupled to the processor is memory that stores the algorithm. In addition, the system comprises a hardware unit that is generally not accessible to the algorithm and an abstraction layer that indirectly facilitates interaction between the hardware unit and the algorithm. The hardware unit comprises one or more physical resources, such as data channels, that are associated by the abstraction layer with a logical resource. In addition, the abstraction layer creates an identifier to the logical resource that may be used by the algorithm. Associated with the identifier is a private state that represents the most recently configured settings of the logical resource. A vector table is used in conjugation with the private state to identify memory locations of optimized command functions that carry out operations associated with the hardware unit. In addition, the vector table is adapted to reflect the run-time state of the system.

Abstract: An IC package includes a package body of non-conductive material. A conductive heat-sink pad includes an interior pad portion located within an interior of the package body. An exterior pad portion is located external to the package body. The exterior pad portion includes at least two pad pieces that are spaced apart to define at least one channel that separates the at least two pad pieces, the at least two pad pieces being electrically connected with each other. The at least two pad pieces may be flush with an underside surface of the package body or one or more of the pad pieces may extend outwardly from the package body.

Abstract: According to one embodiment, a method for compensating for inadequate bit resolution in a light processing system includes receiving a plurality of values each indicative of an intensity level for a pixel to be displayed. Each of the values is represented by a plurality of bits of data. The method also includes determining a quantization step size for the plurality of bits of data. For at least one particular pixel of the pixels, a set of consecutive pixels including the particular pixel is selected. The method also includes determining a difference between the value associated with the particular pixel in the set and each value associated with the other pixels in the set, and also determining that all of the determined differences are less than or equal to the quantization step size. In response, a filtered value for the particular pixel in the set is generated based at least on some of the pixels in the set in addition to the particular pixel.

Abstract: Providing color management includes receiving measurements of the intensity of colors. A light source generates light beams to yield the colors, where the light beams are generated in accordance to image data to create an image. A target color value is established. A duty cycle sequence operable to control the light source is selected in accordance with the measurements and the target color value. Current levels for currents provided to the light source are selected in accordance with the duty cycle sequence and the target color value.

Abstract: The present invention facilitates data recovery without requiring selection of a sample phase. The data is recovered by sampling a received signal to obtain a number of samples at a number of phases over a given time period referred to as a bit time. The samples are analyzed to determine if a transition has occurred in one or more consecutive phases. Such a transition is also referred to as a data toggle. Generally, one or more toggles in a single bit time indicate one data value (e.g., a zero) whereas no transitions indicate another data value (e.g., a one).

Abstract: A semiconductor device has a semiconductor chip with a periphery and an IC organized in a core portion and a peripheral portion. The IC has a top level of interconnecting metal traces (510) from the peripheral portion to the core portion; the traces are covered by an insulating overcoat (520) which has peripheral windows to expose bond pads. The circuit further has at least one level of metal lines (511) on top of the insulating overcoat; the lines lead from the chip periphery towards the chip core, wherein each line (511) is substantially parallel to one of the traces (510) underneath the insulating overcoat and vertically aligned therewith. After assembling the chip onto a leadframe with segments (504), bonding wires (502) connect the bond pads (510a) and the metal lines (511a) with the segments.

Abstract: An apparatus for indicating detection of an onset of a high-voltage condition at an output locus of a signal converter device, the signal converter device including a switching network for switchingly controlling a potential at a circuit node coupled with the output locus in response to a control signal received from a control signal source, includes: (a) a first sensing unit coupled for sensing a parameter at the circuit node; (b) a second sensing unit coupled for sensing the control signal; and (c) a comparing device coupled with the first sensing unit and with the second sensing unit; the comparing device effecting comparison of a first signal from the first sensing unit with a second signal from the second sensing unit. The comparing device effects the detection when the first and second signals have a predetermined relationship, then the apparatus effects the indicating.

Abstract: A low inertia two axis torsional hinged device formed from a single piece of silicon. The two axis torsional hinged device uses a pair of diametrally charged permanent drive magnets to pivot a gimbals member of the assembly about first and second torsional hinges aligned along a first axis. A single drive magnet mounted at the center of the backside of an optical surface of the assembly pivots the optical surface about another pair of torsional hinges aligned along a second axis that is orthogonal to the first axis. The drive magnets mounted on the gimbals member are located on the first axis and the single drive magnet on the back side of the optical surface is mounted at the intersection of the first and second axis such that all three magnets are aligned along the first axis.

Abstract: A disk drive data storage system, comprising a magnetic disk a head for writing data to the disk, and circuitry for providing a first voltage (HWX) to a first node (N1) and a second voltage (HWY) to a second node (N2). The first and second voltage circuitry comprises a first transistor (421P2) of a first type and coupled to the first node, a first transistor (422N2) of a second type and coupled to the second node, a second transistor (441P2) of the first type and coupled to the second node, and a second transistor (442N2) of the second type and coupled to the node. The system also comprises circuitry for providing, during a first time period, a first biasing signal (VNDY) and a second biasing signal (VPDY) and circuitry for providing, during a second time period, a third biasing signal (VNDX) and a fourth biasing signal (VPDX).

Abstract: Disclosed herein is a micromirror array device package having a light blocking area for reducing unexpected light scattering from the surfaces of the posts.

Abstract: A digital system and method of operation is provided in which several processors (400[]) are connected to a shared resource (432). Each processor has a translation lookaside buffer (TLB) (310[]) that contains recently used page entries that each includes an access priority value. Access priority values are assigned to regions of address space, typically pages, according to the program or data that is stored on a given page. Access priority values are maintained in page tables with address translations, such that when a translated page address is loaded into a TLB, the access priority associated with that page is included in the TLB page entry. Arbitration circuitry (430) is connected to receive a request signal from each processor along with an access priority value (353[]) from each TLB in response to the requested address. The arbitration circuitry is operable to schedule access to the shared resource according to the access priority values provided by the TLBs.

Abstract: A nebulization system, which creates a uniform fog of tiny suspended liquid droplets, to lubricate the surfaces of MEMS devices. These droplets fall over the edge of a baffle and are then mixed with an umbrella-like sheet of N2 turbulation gas to generate a uniform cloud of droplets that fill a passivation chamber. The MEMS device is then positioned in this uniform cloud of lubricant droplets for a specified amount of time, thereby uniformly lubricating all the surfaces of the device. The system uses a laser monitoring approach to control the uniformity of the lubricant cloud by providing feedback to the system to control the flow of gases. The system also equalizes the pressure around the sample device seal to prevent gases from entering or exiting the chamber and thereby influencing the environment inside the chamber.

Abstract: A system and method for providing successive approximation, such as can be used by a successive approximation converter or by a coherent undersampling digitizer. The system comprising a memory having a successive approximation value and a comparison system configured to receive and amplify the difference between a test signal and the successive approximation value and to convert the amplified signal to a digital signal. A multi-bit analog to digital convert can be used to convert the amplified signal to a digital signal.

Abstract: A directional controller for a device is provided. The directional controller consists of keypad contacts, a keyboard, and a button. The keypad contacts are on a printed circuit board. The keyboard has more than four keys and each key is disposed adjacent to one of the keypad contacts. The button is operable for pivoting engagement with the more than four keys to promote contact between the more than four keys and the adjacent one of the keypad contacts.

Abstract: The present invention provides a spurious tone suppressor for use with a power supply system. In one embodiment, the spurious tone suppressor includes an error signal generator configured to provide a spur error signal proportional to a spur signal associated with the power supply system. Additionally, the spurious tone suppressor also includes an adaptive spur cancellation engine coupled to the error signal generator and configured to adaptively process the spur error signal and generate a corresponding anti-spur signal that is injected into the power supply system to suppress the spur signal.

Abstract: A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.