Abstract: An improved sub-band speech coding system is provided by subdividing signals into a lower an higher subband, downsampling the lower subband before coding and coding the higher subband without downsampling. The decoder includes decoding and upsampling of the lower subband and decoding the higher subband and adding the higher subband to the lower subband.

Abstract: An apparatus for effecting signal chopping in an amplifier device having an amplifier section, a modulation section, a ramp generating section and a clock section includes: at least one signal treating unit coupled among the clock section, the amplifier section and the ramp generating section. The at least one signal treating unit cooperates with the clock section to effect providing a chopping signal to the amplifying unit at a chopping frequency and to effect providing a ramping signal at a ramping frequency to the ramp generating section. The chopping frequency is neither a fundamental frequency nor a harmonic frequency of the ramping frequency.

Abstract: A method and apparatus for encoding video includes selecting a prediction motion vector for a current block of a current image frame from respective motion vectors of two or more neighbor blocks of the current block. Then the current block and a neighbor block corresponding to said prediction motion vector are checked to determine whether they are motion correlated. Checking motion correlation includes determining that the difference between the best correlation from the correlation of the current block with one or more neighbor blocks and the correlation of the neighbor block with a block in the previous image frame at a location defined by the prediction motion vector fulfils a predetermined criterion.

Abstract: A multilayered torsional hinged mirror assembly that includes a drive/sensing permanent magnet. To allow for permanent magnets having increased thicknesses, a hinge plate of the mirror defines a recess for receiving the permanent magnet. The recess may be etched completely through the hinge plate such that the permanent magnet is bonded to the back side of the mirror layer, or alternately may extend part way through the hinge plate to allow the permanent magnet to be mounted to the bottom of the recess. In both embodiments, the center of mass of the mirror assembly can be adjusted to lie on the pivoting axis of the mirror assembly by selection of the depth of the recess and the shape and mass of the permanent magnet.

Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a bottom laminate substrate (BLS) (130) is formed to include interconnection patterns (IP) (170, 172) coupled to a plurality of conductive bumps (PCB) (130). A top substrate (TS) (140) is formed to mount a top package (110) by forming a polyimide tape (PT) (142) affixed to a metal layer (ML) (144), and a top die (136) attached to the ML (144) on an opposite side as the PT (142). A laminate window frame (LWF) (150), which may be a part of the BLS (130), is fabricated along a periphery of the BLS (130) to form a center cavity (160). The center cavity (160) enclosed by the BLS, the LWF and the TS houses the top die (136) affixed back-to-back to a bottom die (134) that is affixed to the BLS (130). The IP (170, 172) formed in the BLS and the LWS (150) provide the electrical coupling between the ML (144), the top and bottom dies (136, 134), and the PCB (130).

Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a bottom laminate substrate (BLS) (130) is formed to include interconnection patterns (170) coupled to a plurality of conductive bumps (130). A top substrate (TS) (140) is formed as a receptor to mount a top package (110). The TS (140) is formed by a polyimide tape (142) affixed to a metal layer (144). A laminate window frame (LWF) (150), which may be fabricated as a part of the BLS (130), is fabricated along a periphery of the BLS (130) to form a center cavity (160). The center cavity (160) that is enclosed by the BLS (130), the LWF (150) and the TS (140) houses at least one die (134, 136) attached to the BLS (130). The interconnection patterns (170, 172) formed in the BLS (130) and the LWF (150) provide the electrical coupling between the metal layer (144), the at least one die (134, 136), and the plurality of conductive bumps (130).

Abstract: A communication apparatus comprising an audio input device adapted to capture a first audio sample, where the first audio sample comprises a noise component. The apparatus further comprises signal processing logic coupled to the audio input device. If the intensity of the noise component is equal to or greater than the intensity of a voice component of a second audio sample received from a different communication apparatus, the signal processing logic amplifies the voice component.

Abstract: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.

Abstract: A method of conserving power in a WLAN receiver is provided wherein processing tasks that need only to be operated for a brief period of time during the reception of a received packet are enabled only during the brief period of time. The enabling includes providing multiple power control signals that are controlled by a state machine for enabling and disabling the processing tasks.

Abstract: The invention includes a design for device design-for-test and a burn-in-board that reduce the number of external components per device on the board. Inputs to the I/Os of a device from input means are inverted between pairs of output pins. A single resister is coupled between an output that is true (e.g., not inverted) and an output that is inverted. Thus, instead of using one or more resistors per I/O from the DUT, a single resister can be coupled between inverted and non-inverted outputs.

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract: A method provides frequency and phase offset estimation in a SCDMA burst receiver (such as a DOCSIS 2.0 SCDMA burst receiver) by application of the known Least Square (LS) parameter estimation algorithm to a pre-known transmitted sequence, called preamble, in order to optimally characterize the phase and frequency offsets affecting the transmitted data. The LS parameter estimation algorithm is adapted to SCDMA burst receiver specifications by changing index calculations to fit according to SCDMA preamble locations. Improved estimation accuracy can be achieved by using weighted least squares that disregard symbols affected by impulse and burst noise. Weighted least squares can further impart more weight to last symbols to more accurately estimate contemporary impairments. The method is particularly useful for communication systems having large frequency and phase offsets as in the DOCSIS 2.0 SCDMA burst receiver.

Abstract: A system and method for using asymmetric companion codecs to establish and maintain a communication. A communication system endpoint replaces instances of a companion codec with the members of a group of all of the companion codecs for the endpoint and performs appropriate translations of compatible codecs to provide a communication between communication system endpoints.

Abstract: A channel norm-based ordering and whitened decoding technique (lower complexity iterative decoder) for MIMO communication systems performs approximately the same level of performance as an iterative minimum mean squared error decoder. Decoding a signal vector comprises receiving a signal vector yk, multiplying the received signal vector yk by a conjugate transpose of a channel matrix H*. A column vector zk is generated. The entries of the column vector zk are reordered and an estimated channel matrix {tilde over (H)} is generated. The estimated channel matrix {tilde over (H)} decomposed using a Cholesky decomposition and generating a triangular matrix L. Triangular matrix L is solved backwards and a signal vector {tilde over (s)}k estimated. An estimate of the transmitted symbol vector ?k is generated.

Abstract: A CMOS LC-tank oscillator includes a pair of symmetric inductors and a differential pair of transistors. The inductors have a first one of their terminals interconnected at a supply node to which a voltage supply is applied through a supply resistor and a second terminal connected to the drain of a respective one of the transistors. The transistors have their sources interconnected at a tail node which is connected to ground through a tail resistor. A current control loop controls a core current between the supply and tail nodes so as to keep a voltage drop across the tail resistor at a level determined by a reference voltage. The current control loop keeps the core current between the supply and tail nodes at the required level so that a resistor may replace the upstream supply voltage regulator and another resistor may replace the downstream bias regulator. Consequently, sources of noise injected into the LC-tank type oscillator are eliminated.

Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Abstract: A wire feed sensor guide, used in fabrication of semiconductor packages, guides a wire W from a wire source to a wire bonding location. The wire feed sensor guide has a unitary slider 1 that can be manually slid into and out of a fixed portion (2 or 2/3). Slider 1 has a slot SL that guides wire W, and includes a hole S for a sensor wire SW (such as optical fiber) that senses the position of wire W within the slot. Slider 1 also includes an air tube hole A that transmits air to urge wire W from a first position W1 toward a second position W2 during a wire bonding cycle. Advantageously, the unitary nature of the slider (including its air tube hole A and sensor wire hole S) ensure that the air blowing and wire position sensing processes do not require manual adjustment. Moreover, the end of the sensor wire is substantially protected from contamination by being substantially enclosed in the slider 1 and exposed only inside slot SL, thus increasing reliability.

Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A wireless device (10, 12) is provided that distinguishes between multiple piconets. The wireless device (10, 12) includes a preamble component (160, 162, 164, 166) and a correlator (150) component. The preamble component (160, 162, 164, 166) provides a preamble (120) for a wireless fixed frequency interleaving transmission, and the correlator component (150) distinguishes a wireless transmission based on the preamble (120). A circuit (180) is provided for a wireless receiver to despread a hierarchical sequence (120) made by spreading an M-length sequence (110) with an N-length sequence (112). The circuit (180) includes a first and second despreaders (185, 190). The first despreader (185) is coupled to a signal input to despread a received signal. The signal is a fixed frequency interleaved transmission. The second despreader (190) is coupled to an output of the first despreader (185). The second despreader (190) despreads the output of the first despreader (185) with a second sequence.