Abstract: In a method and system for testing a device, a tester is operable to generate a first set of test signals for testing the device. The tester is electrically coupled to a test head, which in turn provides electrical coupling to the device. A test assembly is operable to generate a second set of test signals for testing the device. The test assembly is electrically coupled to an interface apparatus, which is adapted to be removably secured to the test head. The interface apparatus is operable to communicate the first and second set of test signals to the device.

Abstract: Simplifying the design of buffer amplifier circuits to provide reference voltages of desired characteristics on a path. Two separate circuits may be used to provide the necessary charging (of a load connected to the path) in non-overlapping time durations. In an embodiment in which the load comprises sampling capacitors of a stage of an analog to digital converter (ADC), each of the two circuits contains a corresponding charging capacitor, with the charging capacitors charging the load in non-overlapping time durations of a hold phase. The first charging capacitor may be charged using a coarse buffer with a high drive strength and the second charging capacitor may be charged using a fine buffer with high accuracy.

Abstract: A first downlink transmission beam and a second downlink transmission beam is determined based on a received user-derived signal. The first downlink transmission beam is substantially uncorrelated with the second downlink transmission beam. The first downlink transmission beam is associated with a portion within a first sector. The second downlink transmission beam is associated with a portion within a second sector. A first signal is diversity encoded to produce a first diversity-encoded signal. A second signal is diversity encoded to produce a second diversity-encoded signal. The first diversity-encoded signal is sent over the first downlink transmission beam. The second diversity-encoded signal is sent over the second downlink transmission beam.

Abstract: Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.

Abstract: Multiple-mode direct phase/amplitude modulation circuitry (20) for use in a transceiver (17) of a device such as a wireless handset (10) is disclosed. The modulation circuitry (20) includes a modulation loop (36) for modulating a phase signal into a Gaussian-Minimum-Shift-Keyed (GMSK) signal for transmission in a first mode. The modulation loop (36) may include a phase-locked loop (45) with its frequency controlled by a ?-? demodulation of a compensated version of the phase signal, or alternatively may produce a modulated signal from a direct digital synthesis circuit (70; 70?). An amplitude signal is converted into an analog signal and applied to a single-sideband mixer (43) for combination with a frequency multiplied version of the phase-modulated signal (GMSK(t); PH(t)), producing an amplitude and phase modulated signal for transmission in a second mode.

Abstract: An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a deposited layer 505 of nickel/titanium alloy on each of the pads; the alloy has a composition and crystalline structure operable in reversible phase transitions under thermomechanical stress, whereby mechanical strain is absorbed by the alloy layer. Preferably, the alloy has between 55.0 and 56.0 weight % nickel, between 44.0 and 45.0 weight % titanium, and a thickness in the range from 0.3 to 6.0 ?m, recrystallized after deposition in a temperature range from 450 to 600° C. for a time period between 4 and 6 min. A layer 506 of solderable metal is on the alloy, operable as diffusion barrier after reflow attachment.

Abstract: A hybrid PCI_Express fabric system allows LPC bus commands and data to be sent across the PCI_Express fabric from a portable computer to its docking station. This permits the portable computer to be coupled to peripheral devices connected to the docking station without additional connectors on the portable computer and the docking station.

Abstract: A method and system for measuring the temporal response of a micromirror array to a variety of driving signals. A micromirror array is illuminated with a coherent light source so that a diffraction pattern is reflected from the micromirror array. One or more photodetectors are aligned with spots of light in the diffraction pattern that correspond to orders of the diffraction pattern. Diffraction pattern theory predicts that the intensity of these spots of light will vary as the tilt angle of the micromirrors is changed. Thus, by measuring the relative intensity of the spots of light as the micromirror array is provided with a variety of driving signals, many performance characteristics of the micromirror array can be measured. Some of these characteristics include the impulse response, the forced resonant frequency (i.e. the natural frequency), the damped resonant frequency, the quality factor of the micromirror response, the damping factor of the micromirror response, and the frequency transfer function.

Abstract: A method and apparatus for collocating an interface circuit with a disk drive read/write head is described. In one embodiment the interface circuit is attached to the load arm on one side and the miniflex interconnect on the other. The read/write head is mounted on the miniflex directly below the interface circuit. The interface circuit comprises a read signal preamplifier, a write driver, and head selection circuitry. A common multiplexer circuit is used to perform the other conventional read/write circuit functions. The common multiplexer circuit includes a head selection block to determine which heads are activated, a head driver block, and a read receiver block. The common multiplexer circuit is mounted at the base of the miniflex.

Abstract: A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed space between each supporting chip and a next successive vertically stacked chip is described. The device is fabricated by patterning islands of aluminum atop the passivation layer of each supporting chip simultaneously with processing to form bond pad caps. The fabrication process requires no additional cost, and has the advantage of providing standoffs for a plurality of chips by processing in wafer form, thereby avoiding additional assembly costs. Further, the standoffs provide improved thermal dissipation for the device and a uniform, stable bonding surface for wire bonding each of the chips to the substrate.

Abstract: In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.

Abstract: An apparatus is disclosed for allocating processing resources, such as instruction execution which can be measured in MIPs or memory capacity, or other resources of a processor itself or resources used in the process of performing operations, such as memory resources, busses, drivers and the like, to functions in a queue waiting to be executed. This apparatus includes a capacity determining device for determining an amount of the processor resource available to be assigned, a load determining device for determining an estimate of an amount of the resource needed for each function waiting in the queue to execute, a prioritization device for prioritizing each of the functions in the queue waiting to be executed, and an allocating device, which receives information from the capacity determining device, the load determining device, and the prioritization device, for allocating the available resource to the functions based on a hierarchical priority scheme.

Abstract: A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more external devices. The interface accomplishes this function by serializing bus transactions in one device, transferring the serial transaction between devices via one interface port, and de-serializing the transaction in the external device. The general features include low pin count (as few as three signals), simple packet based transfer protocol for memory mapped access, symmetric operation, simple block code formatting, supports both host to peripheral and peer to peer transactions, and support multiple outstanding transactions.

Abstract: A cache system is constructed in accordance with an architecture that comprises a tag array into which tags are stored that are used to determine whether a hit or a miss into the cache system has occurred. Further, the cache system comprises a data array into which cache lines of data are stored, each cache line comprising a plurality of sub-lines, and each sub-line is adapted to be written back to a system memory separate from the other sub-lines. The cache system also comprises a controller coupled to the tag and data arrays. The tag array includes a cache-line dirty bit associated with each cache line and the data array includes a plurality of dirty bits for each cache line. The plurality of dirty bits comprises one sub-line dirty bit for each sub-line.

Abstract: A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector in order to generate the permutation index vector. An index vector generation circuit is also disclosed.

Abstract: Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by nitriding the sidewalls of the gate structure, and a silicon nitride encapsulation layer is formed to protect the conditioned sidewalls during manufacturing processing. The conditioning and encapsulation avoid oxidation of gate stack layers, particularly metal gate layers, and also facilitate repairing or restoring stoichiometry of metal and other gate layers that may be damaged or altered during gate patterning.

Abstract: A write driver output circuit having a programmable output impedance. A plurality of amplifiers are disposed in parallel between an input and an output of an impedance matching section of the write driver circuit and can be selectively enabled to correspondingly set the output impedance of the write driver circuit. The amplifiers may be Class AB amplifiers, each of which have a smaller size than an conventional AB used in a single amplifier write driver circuit. Each of the Class AB amplifiers has a corresponding matching resistor, and a current source, each being selectively enabled and disabled by enabling and disabling, respectively, the corresponding current sources, such as through the use of serial interface bits.

Abstract: The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a drain-extended well (115) having a curved region (125) and a straight region (130) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The transistor (100) further includes a centered source/drain (120) surrounded by the drain-extended well (115) and separated from an outer perimeter (135) of the drain-extended well (115). A separation in the curved region (145) is greater than a separation in the straight region (150). Other embodiments of the present invention include an integrated circuit (300) and a method of manufacturing a transistor (200).

Abstract: A software controlled mechanism causing a test equipment to place the edges of test signals accurately. The mechanism determines expected time of occurrence of an edge of a signal in relation to a tester cycle time. The mechanism sends commands to the test equipment to receive back the signal (of interest) in multiple cycles and provides the time points corresponding to the edge in the multiple cycles. The software controlled mechanism computes an error based on the time points and the expected time, and adjusts the timing of the edges of the signal according to the error. Such computation and adjustment are performed until the error is within an acceptable range.

Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.