Patents Assigned to The U.S. Government as represented by the Director, National Security Agency
  • Patent number: 11444184
    Abstract: A method is disclosed, including positioning a lead wire of a gate chip at a distance of less than 10 nm from a semiconductor heterostructure. The heterostructure includes a surface layer and a subsurface layer. The method also includes inducing an electrostatic potential in the subsurface layer by applying a voltage to the lead wire. The method also includes loading a charge carrier into the subsurface layer. The method also includes detecting the charge carrier in the subsurface layer of the semiconductor heterostructure by emitting a radio-frequency pulse using a resonator coupled to the at least one lead wire of the gate chip, detecting a reflected pulse of the emitted radio-frequency pulse, and determining a phase shift of the reflected pulse relative to the emitted radio-frequency pulse. The method also includes characterizing the quantum dot by measuring valley splitting of the quantum dot.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 13, 2022
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventors: Charles George Tahan, Rousko Todorov Hristov, Yun-Pil Shim, Hilary Hurst
  • Patent number: 11404789
    Abstract: An antenna is disclosed, including an omnidirectional antenna with a first conical antenna section. The omnidirectional antenna forms a first feed aperture. The omnidirectional antenna forms a field of view aperture in a wall of the omnidirectional antenna. The antenna also includes a directional antenna, disposed within an interior portion of the omnidirectional antenna such that the directional antenna has an electrically unobstructed field of view through the field of view aperture in the wall of the omnidirectional antenna. The antenna also includes a feed cable, electrically coupled to the directional antenna and disposed within the omnidirectional antenna and the first feed aperture.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 2, 2022
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventor: Brandan T. Strojny
  • Patent number: 11265012
    Abstract: A method of transmitting a message includes, for each data block, generating a root matrix using a generator, generating a quasi-cyclic matrix H using the root matrix, encoding the block using H to create a codeword, and transmitting the codeword. The root matrix includes three submatrices: an identity matrix in an upper-left-hand portion of the root matrix, an identity matrix in a lower-left-hand portion of the root matrix, and a circulant matrix in a right-hand portion of the root matrix. The circulant matrix equals the sum of an identity matrix and an identity matrix with rows shifted once to the right. Generating H includes expanding the root matrix by replacing 0 elements in the root matrix by a square matrix of 0 elements and replacing 1 elements in the root matrix by a shifted diagonal matrix. Non-zero elements of the diagonal matrix are selected from GF(q) based on the generator.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 1, 2022
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventor: Bradley B. Comar
  • Patent number: 11138500
    Abstract: A computer processor includes an on-chip network and a plurality of tiles. Each tile includes an input circuit to receive a voltage signal from the network, and a crossbar array, including at least one neuron. The neuron includes first and second bit lines, a programmable resistor connecting the voltage signal to the first bit line, and a comparator to receive inputs from the two bit lines and to output a voltage, when a bypass condition is not active. Each tile includes a programming circuit to set a resistance value of the resistor, a pass-through circuit to provide the voltage signal to an input circuit of a first additional tile, when a pass-through condition is active, a bypass circuit to provide values of the bit lines to a second additional tile, when the bypass condition is active; and at least one output circuit to provide an output signal to the network.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 5, 2021
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventor: David J. Mountain
  • Patent number: 10961747
    Abstract: A device for securing a door includes an elongated flat rigid member. A first segment is connected to a second segment by a transition segment perpendicular to the first and second segments. The first segment forms an aperture to admit a restraining device. The device also includes a first blocking member having two apertures and configured to engage the first member such that the restraining device restrains the first blocking member relative to the flat rigid member. The device also includes a second blocking member configured to lockably engage the second segment, thereby securing the device relative to a frame of the door with the first and second segments on opposite sides of the frame. When the device is secured and the door closed, and the first blocking member restrained relative to the flat rigid member, the door is blocked from being opened by the first and second blocking members.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: March 30, 2021
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventors: David A. Myers, Adam S. Wytko
  • Patent number: 10778229
    Abstract: A CNOT gate includes a clock line, splitter, and first and second store-and-launch gates (SNLs) to each output a fluxon in accordance with a clock fluxon and polarities of an input fluxon and the clock fluxon. The CNOT gate also includes first and second IDSN gates. When one fluxon input is received, the IDSN gate outputs one fluxon in accordance with a polarity of the fluxon input. When two fluxon inputs are received, the IDSN gate outputs two fluxons in accordance with an inverse polarity of the fluxon inputs. The CNOT gate also includes first and second NOT gates to receive a fluxon output from the first IDSN gate and output a fluxon of opposite polarity, and a third NOT gate to receive a fluxon output from the second IDSN gate and output a fluxon of opposite polarity.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 15, 2020
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventors: Kevin D. Osborn, Waltraut Wustmann
  • Patent number: 10460212
    Abstract: A method is disclosed for using digital camera fingerprints to create bins of digital images generated by the same digital camera. The method includes determining, for each digital image in the set of digital images, a digital fingerprint. The method also includes sorting each digital image into one of a high-quality subset and a low-quality subset. The method also includes sorting each digital image in the high-quality subset into one of a plurality of bins. In each bin the images were determined, based on the digital fingerprints of the images in the bin, to have been generated by a single digital camera associated with the bin. The method also includes sorting each digital image in the low-quality subset into one of the plurality of bins, the sorting being performed based on the digital fingerprint of the digital image.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 29, 2019
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventors: Sarah T. Charlton, John A. Emanuello
  • Patent number: 7700391
    Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: April 20, 2010
    Assignee: U.S. Government as Represented by the Director, National Security Agency, The
    Inventors: John L. Fitz, Daniel S. Hinkel, Scott C. Horst
  • Patent number: 7492814
    Abstract: Removing noise and interference from a signal by calculating a joint time-frequency domain of the signal, estimating instantaneous frequencies of the joint time-frequency domain, modifying each estimated instantaneous frequency, if necessary, to correspond to a frequency of the joint time-frequency domain to which it most closely compares, redistributing elements within the joint time-frequency domain according to the modified instantaneous frequencies, computing a magnitude for each element in the redistributed joint time-frequency domain, plotting the results, identifying peak values, eliminating from the redistributed joint time-frequency domain elements that do not correspond to the peak values, identifying noise and interference in the peak values, eliminating the noise and the interference from the redistributed joint time-frequency domain elements, and recovering a signal devoid of noise and interference from the modified redistributed joint time-frequency domain.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: February 17, 2009
    Assignee: The U.S. Government as Represented by the Director of the National Security Agency
    Inventor: Douglas J. Nelson
  • Patent number: 5258334
    Abstract: Reverse engineering of integrated circuit devices is prevented by denying visual access to the topology of an integrated circuit device. Visual access is denied by coating the device with an opaque ceramic. The opaque ceramic is produced by first mixing opaque particulate with a silica precursor. The mixture is then applied to the surface of the integrated circuit device. The coated device is heated to a temperature in the range of 50.degree. C. to 450.degree. C. in an inert environment for a time within the range of 1 second to 6 hours to allow the coating to flow across the surface of the device without ceramifying. The coated device is then heated to a temperature in the range of 20.degree. C. to 1000.degree. C. in a reactive environment for a time in the range of 2 to 12 hours to allow the coating to ceramify.
    Type: Grant
    Filed: January 15, 1993
    Date of Patent: November 2, 1993
    Assignee: The U.S. Government as represented by the Director, National Security Agency
    Inventor: Leon Lantz, II
  • Patent number: 4972105
    Abstract: A reprogrammable logic array is characterized by the use of a RAM fuse to selectively control the transfer of variable from input lines to intersecting output combination lines of the array. The configuration of the combiner array is programmed by writing to all of the RAM locations that are associated with the array. If a connection is to be made, a logical "1" is written to the RAM cell for that connection and if no connection is desired, a "0" is written to the RAM cell. The array which includes a novel input interface, can be quickly and easily reprogrammed simply by writing to the appropriate RAM cells. The RAM fuses may function as standard static RAM if the device does not need to function as a combiner.
    Type: Grant
    Filed: September 22, 1989
    Date of Patent: November 20, 1990
    Assignee: The U.S. Government as represented by the Director, National Security Agency
    Inventors: Dennis A. Burton, Wendy L. Goble, Robert D. Morelli, Thomas B. Phelps
  • Patent number: 4928294
    Abstract: An improved asymmetric crystal topography x-ray imaging system employing a ine focus horizontal line source of x-rays and a crystal monochromator used in a compression mode. Relatively large horizontal and vertical dimensions of the monochromating crystal allow imaging of larger areas of imperfect crystals than previously possible, without adversely affecting image resolution. The high resolution two-dimensional images are a direct consequence of our method of controlling the probe beam divergences. An appreciably enhanced and useful intensity of monochromatic x-rays is obtained over that available with prior asymmetric crystal topography systems.
    Type: Grant
    Filed: March 24, 1989
    Date of Patent: May 22, 1990
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventors: Warren T. Beard, Jr., Ronald W. Armstrong
  • Patent number: 4825442
    Abstract: An optically controlled laser device is used to perform digital logic functions. The device comprises a single mode semiconductor laser including a waveguide for coupling light into the lasing caving at an angle at or near normal incidence with respect to the laser radiation generated by the laser. The single mode properties of the laser are achieved by index guiding. The coupled light interacts with the laser radiation in a small region of the lasing cavity creating a perturbation that quenches the laser output, whereby input of the coupled light enables the laser device to perform logic functions.
    Type: Grant
    Filed: April 19, 1988
    Date of Patent: April 25, 1989
    Assignee: U.S. Government as represented by Director, National Security Agency
    Inventor: John L. Fitz
  • Patent number: 4818949
    Abstract: An apparatus is described which performs real time spectrum analysis of large bandwidth radio frequency signals. The apparatus allows the simultaneous monitoring of all frequencies within the band of interest, and operates in the presence of multiple frequencies.
    Type: Grant
    Filed: January 6, 1988
    Date of Patent: April 4, 1989
    Assignee: U.S. Government as represented by Director, National Security Agency
    Inventor: Jonathan D. Cohen
  • Patent number: 4357549
    Abstract: An apparatus for altering frequencies such that any one of a plurality of input frequencies automatically becomes another specified frequency. The value of the output frequency will remain constant regardless of which input frequency chosen, as long as the input frequencies have the relationship a, 2a, 4a, 8a . . . An input signal is received by a descending cascade of units composed of multipliers and filters. The multiplier portion of each unit must be in series with and receive the input stimuli before the filter portion of each unit. Each multiplier portion of the unit must also have a control input of a predetermined value. A phase lock loop inside of a feedback loop compensates for instantaneous variations of frequency in the input signal. This feedback loop is connected from the multiplier-filter unit to the control input for each multiplier portion.
    Type: Grant
    Filed: December 2, 1980
    Date of Patent: November 2, 1982
    Assignee: U.S. Government as represented by the director of National Security Agency
    Inventor: Kelly A. Miller