Abstract: A computer system having a plurality of processors with each processor having associated therewith a cache memory is disclosed. When it becomes necessary for a processor to update its cache with a block of data from main memory, such a block of data is simultaneously loaded into each appropriate cache. Thus, each processor subsequently requiring such updated block of data may retrieve the block from its own cache, and not be required to access main memory.

Abstract: A message is generated at each of a plurality of source nodes, each message comprising at least address information identifying a first or destination node Di, and address information identifying a source node Si. The address information for the destination node is then used to route each message through the nodes of the communication network toward its destination node. At each node where two messages meet that are addressed to the same destination node, a second two messages are generated in place of the first two messages. One of these messages is routed toward the destination node while the other is routed toward an auxiliary node Ai whose address is specified in the message. If any further collisions take place between two messages routed to the same destination node, again two more messages are generated in place of the two colliding messages and one is routed toward the destination node while the other is routed toward another auxiliary node.

Abstract: A method is described for simulating a hexagonal array of computer processors or memories in a computer in which the processor and/or memories are physically connected in a rectilinear grid. The grid provides for communication between adjacent processors in both the horizontal and vertical directions. Thus, it provides physical connections between each processor and four nearest neighbor processors. Each processor is provided with two additional nearest neighbor processors by providing communication between each processor of the array and two additional adjacent processors located on different diagonals in the array. As a result of this arrangement the two additional processors are located either in the same column but in different rows adjacent to the row in which the neighboring processor is located or they are in the same row but in different columns adjacent to the column in which the neighboring processor is located.

Abstract: In accordance with the invention, each element or mode in the n-dimensional connection pattern is assigned a unique binary number or address by numbering the elements. Next, the individual binary digits of the address associated with each element are assigned to the different dimensions of the connection pattern of m dimension according to a fixed rule. Each set of binary digits that is so assigned to a dimension is then treated as the address of the node in that dimension in a gray code space; and the nodes that are its nearest neighbors in that dimension are those nodes that bear the Gray code values immediately before it and immediately after it in the Gray code sequence. Data are then routed to the nearest neighbor in one direction in a dimension by forwarding them from one node to the node bearing the next succeeding (or preceding) Gray code address and a node can be conditioned to receive such data by having it look for data from the node with the next preceding (or succeeding) address.

Abstract: A parallel processor array is disclosed comprising an array of processor/memories and means for interconnecting these processor/memories in an n-dimensional pattern having at least 2.sup.n nodes through which data may be routed from any processor/memory in the array to any other processor/memory. Each processor/memory comprises a read/write memory and a processor for producing an output depending at least in part on data read from the read/write memory and on instruction information. The interconnecting means comprises means for generating an address message packet that is routed from one processor/memory to another in accordance with address information in the message packet and a synchronized routing circuit at each node in the n-dimensional pattern for routing message packets in accordance with the address information in the packets.

Abstract: A method of detecting bit errors in a possibly corrupted version of an original data word, the bits of the original data word (e.g., a 32-bit data word) being organized in nibbles of four bits each, each nibble being stored in a single four-bit memory chip. In the method, the unique combinations of data word bits used for deriving a first set of check bits are chosen so that the existence of any three bit errors or four bit errors within a single nibble of the possibly corrupted version will be detectable based on a first set of syndrome bits formed by comparing each original check bit of the first set with a corresponding new check bit.

Abstract: A message packet router is described that performs the functions of determining if a message packet is addressed to circuitry associated with the router, of routing message packets to their distination if possible and of storing message packets that cannot be routed on because of circuit conflicts. The router also provides additional functions of merging message packets addressed to the same destination, of saving the state of the router at each significant point in the message routing cycle, and of running the entire routing cycle backwards. This later feature makes it possible to broadcast message packets selectively to certain processors in the array.

Abstract: A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. The ECC circuit generates an error correction code for each block of data to be stored in the system and supplies this code along with the block of data to the memory units for storage. The system further comprises means for generating from a sequence of blocks of data and associated error correction codes retrieved from these memory units a sequence of bits which correct an error in the information retrieved from one memory unit and means for writing this sequence of correction bits to the spare read/write memory unit. Advantageously, the system also comprises means for rewriting the sequence of correction bits to a memory unit after a faulty memory unit has been repaired or replaced.

Abstract: A printed circuit board interconnect system having flat or ribbon cable folded in a pattern and supported in that pattern so that a large number of boards in an upper rack can be connected each by a respective cable to corresponding boards among a large number of boards in a lower rack in an orderly fashion while preserving the pin orientation for the boards. The cables are each folded at the ends in right angle bends that convert the horizontal direction to vertical but reverses the conductor orientation. In a central portion of the vertical extending cable, it is folded in two further right angle bends and mid way between them with a 180 degree bend. The central bend reestablishes the conductor orientation. A multi-row comb serves to support the ribbon cable in the central region and keep one cable separate from another.

Abstract: A video system for exposing a video camera to a field of view through a sequence of different filter elements. A position detection system is employed in order to identify which filter element is in the field of view without requiring synchronization between the filter elements and the camera system. The filter elements are rotated on a wheel in front of the camera lens by an unsynchronized motor, and wheel position is detected and used to trigger a frame buffer so that it fills with signals from a camera view through a particular unitary filter. The position detection system may include a coded marking on the wheel which is detected by a separate sensor or detection in the signal stream from the camera, or it may include means for sensing the filter characteristic in the video signal itself. A controller provides a request of video signals for a particular filter characteristic which operates in synchronism with the position sensor.

Abstract: A method to operate on a single instruction multiple data (SIMD) computer for searching for relevant documents in a database which makes it possible to perform thousands of operations in parallel. The words of each document are stored by surrogate coding in tables in one or more of the processors of the SIMD computer. To determine which documents of the database contain a word that is the subject of a query, a query is broadcast from a central computer to all the processors and the query operations are simultaneously performed on the documents stored in each processor. The results of the query are then returned to the central computer. After all the search words have been broadcast to the processors and point values accumulated as appropriate, the point values associated with each document are reported to the central computer. The documents with the largest point values are then ascertained and their identification is provided to the user.

Abstract: A virtual processor mechanism and specific techniques and instructions for utilizing such virtual processor mechanism within an SIMD computer having numerous processors, and each physical processor having dedicated memory associated therewith. Each physical processor is used to simulate multiple "virtual" processors, with each physical processor simulating the same number of virtual processors. The memory of each physical processor is divided into n regions of equal size, each such region being allocated to one virtual processor, where n is the number of virtual processors simulated by each physical processor. Whenever an instruction is processed, each physical processor is time-sliced among the virtual memory regions, performing the operation first as one virtual processor, then another, until the operation has been performed for all virtual processors. Physical processors are switched among the virtual processors in a completely regular, predictable, deterministic fashion.

Abstract: A method and apparatus are disclosed for using cellular automata to simulate systems described by partial differential equations such as those that describe the flow of fluid, diffusion or heat transfer. A two-dimensional space is tessellated into a cellular array of regular hexagons. Flow or diffusion into a cell through each of its six sides from each of its six nearest neighbor cells is represented by a value 1; and any other condition is represented by a value 0. A set of rules specifies the effect of such inward flow in terms of an outward flow through at least some of the same six sides of each cell to its nearest neighbors. Interaction of the flow with a surface or other inhomogeneity is simulated by using a different set of rules to specify the outward flow produced when an inward flow encounters a surface or other inhomogeneity in the cell. Outward flow from one cell is an inward flow into its nearest neighbors; and with the next "tick" of the clock of the mode, the cycle repeats itself.

Abstract: A massively parallel processor comprising 65,534 (=2.sup.16) individual processors is organized so that there are 16 (=2.sup.4) individual processors on each of 4,096 (=2.sup.12) integrated circuits. The integrated circuits are interconnected in the form of a Boolean cube of 12 dimensions for routing of message packets. Each circuit board carries 32 (=2.sup.5) integrated circuits and each backplane carries 16 (=2.sup.4) circuit boards. There are eight (=2.sup.3) backplanes advantageously arranged in a cube that is 2.times.2.times.2. Each integrated circuit on a circuit board is connected to five integrated circuits on the same board which are its nearest neighbors in the first five dimensions. Further, each integrated circuit is also connected to four other integrated circuits on different circuit boards, but on the same backplane. Finally, each integrated circuit is also connected to three other integrated circuits, each on a different backplane.

Abstract: A method and apparatus are described for error control and correction which operates across multiple processors and multiple computer memories. In accordance with the invention, data signals from a plurality of processors are applied in parallel to a syndrome generator that generates a syndrome related to such signals. The syndrome is then stored in parallel in a plurality of read/write memories at the same address as the data signals from which the syndrome was generated. When the data signals are read from memory, they are again provided to the syndrome generator which again generates a new syndrome. At the same time the old syndrome signals stored at the same memory addresses are read from memory and compared with the new syndrome. If the two syndromes are the same, there is no error and the data signals are valid. If the syndromes are different, a syndrome decoder determines if sufficient information is available in the syndrome signals to correct the error and does so if it can.

Abstract: A system for error correction in the reading and writing of data to memory in a multiprocessor environment such as a parallel processor. The data written to and read from memory for each processor is channeled through a single error correcting system which effectively treats the data for plural memories associated with plural processors as a single data word and generates a single error correcting code for that combined data word. By applying a single error correcting methodology to a plurality of memories and associated processors, far greater efficiency is achieved in the parallel processor environment. The read and write operations for the plural memories must be accomplished substantially simultaneously in order that the read and write operations can be treated as acting on a single word and a single error correcting code generated.

Abstract: A bistable zero insertion force connector assembly including one or more conductive contact members. Each conductive contact member includes mating ends or contact arms having contact surfaces and a resilient central segment. Variable engagement means cooperates with each conductive contact member to displace the member from a first stable state to a second stable state and vice versa, with minimal force the member being maintained in the first or second stable states by means of stresses induced in the resilient central segment. In the first stable state the contact surfaces of the mating ends or contact arms are disposed in mating proximity to the contact surfaces of the device to be electrically connected therewith with zero force/zero contact while in the second stable state there is secured engagement between the respective contact surfaces. Wiping contact between the respective contact surfaces during transition between the first and second stable states enhance reliability of the electrical connection.

Abstract: A method is described for simulating additional processors in a SIMD computer by dividing the memory associated with each processor into a plurality of sub-memories and then operating on each sub-memory in succession as if it were associated with a separate processor. Thus, a first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at a first location or locations in the first sub-memory. Thereafter, the same first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at the same first location in a second sub-memory. And so forth for each of the sub-memories. By operating a SIMD computer in this fashion, it is possible in effect to vary the number of processors in the array so as to provide the number of processors required for a problem.