Patents Assigned to TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
  • Patent number: 10984825
    Abstract: A head suspension assembly includes a support plate, an interconnection member including a metal plate on the support plate, a first insulating layer on the metal plate, a conductive layer on the first insulating layer and forming a pair of connection pads, and a second insulating layer on the conductive layer, a head mounted in the interconnection member, and a piezoelectric element electrically connected to the connection pads and configured to displace the head when a predetermined voltage is applied across the connection pads. At least one opening is formed in each of the connection pads. The piezoelectric element is electrically connected to each of the connection pads by a conductive adhesive that is between the piezoelectric element and each of the connection pads and filled in the opening.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: April 20, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yasuo Suzuki
  • Patent number: 10984827
    Abstract: According to one embodiment, there is provided a hard disk drive including a first recording surface, a second recording surface, a first magnetic head, a first actuator and a second actuator that move the first magnetic head, a second magnetic head, a third actuator and a fourth actuator that move the second magnetic head, a fifth actuator that moves the second actuator and the fourth actuator, a drive circuit that implements at least one of a first mode in which the second actuator and the fourth actuator operate differently from each other or a second mode in which the first and third actuators operate differently from each other, and a controller that controls the drive circuit.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 20, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Koichiro Miyamoto, Kenichiro Oozeki, Yu Chen
  • Patent number: 10986291
    Abstract: A solid-state image pickup device according to an embodiment is a solid-state image pickup device including a first pixel row, a second pixel row, and a third pixel row that are arranged in a horizontal direction. In the solid-state image pickup device, a first control pulse for transferring charges of first accumulation portions of the fourth and sixth CCD registers in a vertical direction perpendicular to the horizontal direction and a second control pulse for transferring charges of second accumulation portions of the fourth and sixth CCD registers in the horizontal direction are input to the fourth and sixth CCD registers such that an Hi period of the first control pulse and an Hi period of the second control pulse do not overlap each other in a timing period in which charges accumulated in the first, second, and third pixel rows are transferred.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: April 20, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Masao Takahashi
  • Patent number: 10985104
    Abstract: A semiconductor device according to an embodiment includes a first electrode pad containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; an electrode layer containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; and a semiconductor layer provided between the first electrode pad and the electrode layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: April 20, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Seiji Inumiya, Kyoichi Suguro
  • Patent number: 10985268
    Abstract: A semiconductor device includes a semiconductor substrate including first and second surfaces, and a first semiconductor layer of a first conductivity type, a first electrode on the first surface, a first control electrode that is inwardly from the first surface and electrically insulated from the semiconductor substrate and the first electrode, a second control electrode that is inwardly from the first surface, electrically insulated from the semiconductor substrate and the first electrode via a fourth insulating film, and biased independently from the first control electrode, a third control electrode on the second surface and electrically insulated from the semiconductor substrate, and a second electrode on the second surface and electrically connected to the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: April 20, 2021
    Assignees: KABUSH1 KI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoko Matsudai, Yoko Iwakaji
  • Patent number: 10984820
    Abstract: According to one embodiment, a magnetic disk device includes a disk, a head including a first write head and a second write head configured to write data to the disk and a read head configured to read data from the disk, and a controller configured to write write data to a first area of the disk with the first write head and to overwrite the write data written with the first write head in the first area with the second write head.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 20, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroshi Isokawa
  • Patent number: 10984256
    Abstract: According to one embodiment, a recognition device includes a hardware processor. The hardware processor is configured to identify presence or absence of composition elements of a target from input observation data, acquire setting information indicative of a relationship between a type and composition elements, and identify a type of the target based on the setting information acquired and the presence or absence of the composition elements.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 20, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoki Watanabe, Yan Song
  • Patent number: 10984826
    Abstract: A magnetic disk device includes a magnetic disk, a first read element, a second read element, and a controller. In the magnetic disk, first servo information is written. The controller controls the servo writing of second servo information on the magnetic disk, based on the first servo information. In addition, the controller controls acquisition of the first servo information by the first read element. The controller switches a read element to be used to control the servo writing from the first read element to the second read element based on quality of the first servo information acquired by the first read element.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 20, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Tani, Hiroyuki Suzuki
  • Patent number: 10985772
    Abstract: According to one embodiment, a semiconductor integrated circuit 1 includes a sample and hold circuit and a clock generation circuit. The sample and hold circuit has a device with a first withstand voltage and a device with a second withstand voltage that is higher than the first withstand voltage. The clock generation circuit generates a first clock signal to be supplied to the first withstand voltage device and generates a second clock signal to be supplied to the second withstand voltage device based on the first clock signal. The clock generation circuit has a delay adjustment circuit that performs adjustment to delay the second clock signal and bring a phase of the second clock signal close to a phase of the first clock signal in the generation of the second clock signal.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 20, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Naoya Waki
  • Patent number: 10978588
    Abstract: A semiconductor device includes a semiconductor part between first and second electrodes, first and second control electrodes between the semiconductor part and the second electrode. The semiconductor part includes a first region and a second region around the first region. The semiconductor part includes first and third layers of a first conductivity type and second layers of a second conductivity type. The second layers are provided between the first layer and the second electrode. A second layer faces the first control electrode in the second region. Another second layer faces the second control electrode in the second region. A third layer is provided between the second layer and the second electrode. Another third layer is provided between another second layer and the second electrode. The second layer includes a second conductivity type impurity with a concentration lower than that of a second conductivity type impurity in another second layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 13, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shunsuke Nitta, Takeru Matsuoka, Hiroshi Ohta
  • Patent number: 10978098
    Abstract: According to the embodiment, a magnetic recording device includes a magnetic head, a magnetic recording medium, and an electrical circuit. The magnetic head includes a magnetic pole, a first shield, and a stacked body provided between the magnetic pole and the first shield. The stacked body includes first, and second magnetic layers, first, second, and third nonmagnetic layers. An electrical resistance of the stacked body is a first resistance when a current flowing in the stacked body is a first current. The electrical resistance is a second resistance when the current flowing in the stacked body is a second current. The electrical resistance oscillates when the current flowing in the stacked body is a third current. The electrical circuit is configured to supply the second current to the stacked body in a recording operation of using the magnetic head to record information in the magnetic recording medium.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 13, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICE & STORAGE CORPORATION
    Inventors: Naoyuki Narita, Masayuki Takagishi, Hirofumi Suto, Hitoshi Iwasaki, Tazumi Nagasawa, Tomoyuki Maeda
  • Patent number: 10977816
    Abstract: An image processing apparatus includes a calculation circuit configured to calculate a disparity between images, a determination circuit configured to determine a pixel position at which intensive disparity retrieval is to be performed based on distribution statistics of the disparity, an interpolation circuit configured to generate an interpolated image by performing interpolation at pixel positions at which intensive disparity retrieval is to be performed, and an output circuit configured to output a corrected disparity with which the distance to the object is determined. The calculation circuit calculates a first disparity based on the first and second images and generate distribution statistics from the first disparity in the first image, and calculates a second disparity based on the second image and the interpolated image generated from the first image by the interpolation circuit. The output circuit generates the corrected disparity based on differences between the first and second disparities.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: April 13, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Toru Sano
  • Publication number: 20210104257
    Abstract: According to one embodiment, a magnetic recording device includes a magnetic head, and an electrical circuit. The magnetic head includes a magnetic pole, a first shield, and a stacked body provided between the magnetic pole and the first shield. The stacked body includes a first magnetic layer, a second magnetic layer, a first layer provided between the first and second magnetic layers, and a first nonmagnetic layer provided between the first magnetic layer and the first layer. A change rate of an electrical resistance of the stacked body with respect to a change of a current density flowing in the stacked body has a first value when the current density is in a first range, a second value when the current density is in a second range, and a third value when the current density is in a third range.
    Type: Application
    Filed: September 9, 2020
    Publication date: April 8, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hitoshi IWASAKI, Masayuki TAKAGISHI, Naoyuki NARITA, Tazumi NAGASAWA, Hirofumi SUTO
  • Patent number: 10972049
    Abstract: An oscillation apparatus includes a correction circuitry including a first amplifier and a second amplifier, and an oscillation circuitry. The first amplifier amplifies a difference between a first voltage having a first temperature characteristic and a second voltage having a second temperature characteristic different from the first temperature characteristic to generate a third voltage having a third temperature characteristic different from both the first temperature characteristic and the second temperature characteristic. The second amplifier amplifies a difference between a sum of the second voltage and the third voltage, and, a feedback voltage, to generate a fourth voltage which corrects an oscillation frequency of an oscillation voltage. The oscillation circuitry outputs the oscillation voltage controlled in frequency based on the fourth voltage.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: April 6, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroyuki Suwabe
  • Patent number: 10971621
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and first and second control electrodes. The first and second electrodes are provided on the semiconductor body. The first and second control electrodes each include a first portion positioned between the semiconductor body and the first electrode, a second portion positioned between the semiconductor body and the second electrode, and a third portion linked to the first and second portions. The semiconductor body includes first to fourth semiconductor layers. The second semiconductor layer is provided on the first semiconductor layer, and extends along the first to third portions. The fourth semiconductor layer is provided selectively on the second semiconductor layer, and extends along the second and third portions. The fourth semiconductor layer includes second conductivity-type impurities with a higher concentration than a concentration of second conductivity-type impurities in the second semiconductor layer.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: April 6, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Katou, Tatsuya Nishiwaki, Kohei Oasa, Toshifumi Nishiguchi
  • Patent number: 10971623
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes and a control electrode. The semiconductor body is positioned between the first and second electrodes. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes a first layer of a first conductivity-type and a second layer of a second conductivity-type alternately arranged along the first electrode. The first and second layers include first and second low-concentration portions, respectively. The first low-concentration portion has a first conductivity-type impurity concentration lower than that in other portion of the first layer. The second low-concentration portion has a second conductivity-type impurity concentration lower than that in other portion of the second layer. The first low-concentration portion is positioned at a level same as a level of the second low-concentration portion in a direction directed toward the first electrode from the second electrode.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: April 6, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Takuo Kikuchi
  • Patent number: 10969426
    Abstract: A semiconductor integrated circuit includes abnormality detectors configured to detect abnormalities in the semiconductor integrated circuit, and a reference voltage output circuit. The reference voltage output circuit includes switches controlled in accordance with detection signals from the abnormality detectors. The reference voltage output circuit is configured to output as an error signal, a reference voltage having one of a plurality of different values depending on conduction states of the switches of the reference voltage output circuit.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 6, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tsuneyuki Hayashi
  • Patent number: 10964802
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira Mukai, Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Patent number: 10963344
    Abstract: An information processing circuitry includes a storage data generation circuitry, a storage circuitry, a comparison data generation circuitry, and a data comparison circuitry. The storage data generation circuitry is configured to add redundancy bits and a write flag indicating that writing has been made, to input data to generate storage data. The storage circuitry is configured to store the storage data. The comparison data generation circuitry is configured to generate redundancy bits from data stored in the storage circuitry and address accessing to the storage circuitry. The data comparison circuitry is configured to compare the redundancy bits added by the storage data generation circuitry with the redundancy bits generated by the comparison data generation circuitry to execute error detection based on a comparison result and on the write flag.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masashi Jobashi
  • Patent number: 10964343
    Abstract: According to one embodiment, a disk device includes two magnetic disks opposing each other at intervals of 1.2 to 1.5 mm, and at least two suspension assemblies movable respectively between the two magnetic disks. Each of the suspension assemblies includes a base plate, a load beam extending from the base plate, a tab extending from a distal end of the load beam, a wiring member on the load beam and the base plate, including a gimbal portion, and a magnetic head on the gimbal portion, abutting on a dimple of the load beam via the gimbal portion. The ratio of a distance from a bendable location of the load beam to a center of the dimple with respect to a distance from the center of the dimple to a tip of the tab is 2.8 to 3.8.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 30, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Manabu Uehara