Patents Assigned to TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
  • Patent number: 10667395
    Abstract: According to one embodiment, an interposer substrate for switching wiring lines, includes a substrate body having through holes penetrating from a first main surface thereof to a second main surface, through-conductive portions provided respectively in the through holes, grouped into first groups and second groups different from the first groups, first wiring lines each provided on the first main surface and for a respective one of the first groups, second wiring lines each provided on the second main surface and for a respective one of the second groups, first terminals provided on the first main surface and connected respectively to the first wiring lines, and second terminals provided on the second main surface and connected respectively to the second wiring lines.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 26, 2020
    Assignee: Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryoji Ninomiya, Kenichi Agawa
  • Patent number: 10586587
    Abstract: According to one embodiment, semiconductor memory device includes a first circuit that determines data stored in a memory cell; and a second circuit that controls the first circuit, wherein in a sequence in which the second circuit writes first data in the memory cell, the first circuit generates a first current of a first current value, and determines data stored in the memory cell based on the first current and a second current flowing in the memory cell, and in a sequence in which the second circuit writes second data different from the first data in the memory cell, the first circuit generates a third current of a second current value different from the first current value, and determines data stored in the memory cell based on the third current and the second current.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 10, 2020
    Assignees: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiaki Dozaka
  • Patent number: 10566123
    Abstract: A linear solenoid driving device that drives a linear solenoid, the linear solenoid driving device includes a driving circuit that performs switching control over a switching element connected to the linear solenoid based on a driving command; a current detection circuit that has a detection resistor which is connected to the switching element and the linear solenoid, and detects a current, and an operational amplifier which amplifies a voltage across both ends of the detection resistor and outputs the amplified voltage; a reference voltage output circuit that outputs a reference voltage which has a same temperature characteristic as an output voltage of the operational amplifier; and a control unit.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 18, 2020
    Assignees: AISIN AW CO., LTD., TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroyuki Sugiyama, Toshio Shiramatsu
  • Patent number: 10566219
    Abstract: According to one embodiment, a chip transfer member includes a light-transmitting portion and a metal portion. The light-transmitting portion has a light incident surface, a light-emitting surface, and a side surface. The metal portion is provided at the side surface of the light-transmitting portion.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yoichiro Kurita, Tomoyuki Abe, Hideto Furuyama
  • Patent number: 10546601
    Abstract: A method of setting an upper limit value of the number of write times, which is applied to a magnetic disk device including a disk and a head configured to write data to the disk and read the data from the disk, includes measuring a plurality of bit error rates in a recording area of the disk upon repeatedly writing to an area of the disk adjacent to the recording area a number of write times, deriving a function that approximates a bit error rate in relation to a number of write times, using the measured bit rates corresponding to at least a first number of write times, a second number of write times, and a third number of write times, and applying the function to determine a number of write times that correspond to a first threshold bit error rate that makes the data on the disk unreadable, and setting the determined number of write times as the upper limit value of the number of write times.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 28, 2020
    Assignees: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazuhito Ichihara
  • Patent number: 10471984
    Abstract: An electronic control unit where an external watch dog timer (WDT) can always normally detect an abnormality (a failure) to a micro controller unit (MCU) related to a built-in self-test (BIST) function and which can maintain safety of a system. The control unit includes an external WDT to detect an abnormality of the MCU, a reset circuit to reset the MCU when the external WDT detects the abnormality of the MCU, and an ON/OFF control section to turn a gate of the semiconductor switching device on or off in accordance with the external WDT. The inverter is stopped by turning the gate off via the ON/OFF control section when the external WDT is a disable state. When the abnormality of the MCU is not detected in an enable state, the inverter is driven by turning the gate on via the ON/OFF control section. When the abnormality of the MCU is detected, the inverter is stopped by turning the gate off via the ON/OFF control section and the MCU is reset by the reset circuit.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 12, 2019
    Assignees: NSK LTD., TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shin Kumagai, Nobuhiko Ando, Kyosho Uryu, Takahiro Yamazaki
  • Publication number: 20190295577
    Abstract: According to one embodiment, a magnetic disk device includes a disk including a first region and a second region different from the first region, a head that writes data on the disk and reads data from the disk, an actuator that positions the head on the disk, and a controller which positions the head by driving the actuator and writes data in the first region and the second region with the head, a skew angle of the head with respect to a circumferential direction of the disk varying within a first angle in the first region, and varying, in the second region, from a second angle larger than the first angle to a third angle larger than the first angle and the second angle.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Electronic Devices & Storage Corporation
    Inventors: Daisuke Sudo, Tatsurou Sasamoto, Takeyori Hara, Akihiko Takeo, Kazuo Chokki, Tatsuo Nitta
  • Publication number: 20190279672
    Abstract: According to one embodiment, a magnetic disk device includes a base that includes a bottom wall and side walls standing along a circumference of the bottom wall, a housing that includes a cover facing the bottom wall and closing the base, an actuator assembly that is housed inside the housing and is rotatable around a rotation axis, a head movably supported by the actuator assembly, a control circuit board provided outside of the housing, a first sensor disposed on the control circuit board, and a second sensor disposed inside the housing.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 12, 2019
    Applicant: Toshiba Electronic Devices & Storage Corporation
    Inventor: Norio Yoshikawa
  • Publication number: 20190272989
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes generating a plasma of a first gas containing a nitrogen gas and an ammonia gas, supplying a second gas containing nitrogen-containing radicals produced by generating the plasma of the first gas, to a substrate, supplying an organic metal gas containing a group III metallic element to the substrate, and forming a group III nitride semiconductor layer on the substrate by the second gas and the organic metal gas.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 5, 2019
    Applicant: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: YASUHIRO ISOBE, NAOHARU SUGIYAMA, Takayuki SAKAI, Kyoichi Suguro
  • Publication number: 20190271083
    Abstract: According to one embodiment, a film formation apparatus includes a substrate support member, a first gas supplier disposed above the substrate support member and supplying a first gas, a second gas supplier disposed between the substrate support member and the first gas supplier and supplying a second gas, and a plate member disposed between the first gas supplier and the second gas supplier and having a hole, the plate member defining a plasma generation area between the first gas supplier and the plate member, the plasma generation area generating plasma of the first gas, wherein the hole has a diameter between 0.1 to 2 mm and a depth between 0.1 to 5 mm.
    Type: Application
    Filed: September 7, 2018
    Publication date: September 5, 2019
    Applicant: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yasuhiro ISOBE, Naoharu SUGIYAMA, Takayuki SAKAI, Masaaki ONOMURA
  • Publication number: 20190252219
    Abstract: According to one embodiment, a chip transfer member includes a light-transmitting portion and a metal portion. The light-transmitting portion has a light incident surface, a light-emitting surface, and a side surface. The metal portion is provided at the side surface of the light-transmitting portion.
    Type: Application
    Filed: September 12, 2018
    Publication date: August 15, 2019
    Applicants: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, AYUMI INDUSTRIES COMPANY LIMITED
    Inventors: Yoichiro KURITA, Tomoyuki ABE, Hideto FURUYAMA
  • Publication number: 20190198050
    Abstract: According to one embodiment, a magnetic disk device includes a disk, a head including a write head and a first and a second read head, and a controller configured to generate a correction value based on placement information on the write head and the first and the second read head, a first distance between the first read head and the second read head in a case where the first read head is placed at a first position of the disk, and a second distance between the first read head and the second read head in a case where the first read head is placed at the first position, and to correct positions of the heads based on the correction value in a case where first data written with the first
    Type: Application
    Filed: August 27, 2018
    Publication date: June 27, 2019
    Applicant: Toshiba Electronic Devices & Storage Corporation
    Inventors: Naoki Tagami, Takeyori Hara, Gaku Koizumi
  • Patent number: 10282317
    Abstract: According to one embodiment, a semiconductor integrated circuit includes a bus master, a bus slave and a clock gating circuit. The bus master outputs an access request. The bus slave transmits a response to the access request to the bus master. The clock gating circuit shuts off clocks supplied to the bus slave. The bus slave includes a control circuit which outputs first and second signals in response to the access request; a first circuit which outputs a third signal in response to a clock supplied from the clock gating circuit, when the first signal is asserted; and a second circuit which receives the third signal output from the first circuit and the second signal, and outputs a fourth signal as the response to the bus master, when the second signal is asserted.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 7, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuji Hisamatsu
  • Patent number: 10277232
    Abstract: A charge pump circuit of an embodiment includes a current mirror circuit, a first drive switch, a capacitor and a switch circuit. The current mirror circuit causes a current obtained by mirroring a reference current to flow to a first output terminal and a second output terminal. The first drive switch connects or disconnects the first output terminal and a charge pump output terminal. The switch circuit connects the capacitor either to a discharge path between the second output terminal and a node which provides a predetermined voltage or to a charge path between the charge pump output terminal and a GND.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 30, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Go Urakawa, Tsuneo Suzuki
  • Patent number: 10263625
    Abstract: A TDC circuit includes a plurality of delay elements connected in series. The TDC circuit includes a reference signal supply circuit that randomly selects one of the plurality of delay elements to supply a reference signal. The TDC circuit includes a plurality of latch circuits that latch a clock signal in response to outputs of the plurality of delay elements. The TDC circuit includes an output circuit that codes output signals output from the plurality of latch circuits and outputs a digital code indicating a relative time relationship of the clock signal with respect to the reference signal.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 16, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Takashi Tokairin
  • Patent number: 10249327
    Abstract: A disk device includes a recording medium on which data is recorded, a decoding circuit configured to decode data read from the recording medium, and a control circuit. The control circuit is configured to cause first data associated with a target sector referenced in a read request to be read from a target track of the recording medium, second data associated with a non-target sector that is not referenced in the read request to be read from the recording medium after the first data is read from the recording medium, and decoding of the first data to be completed by the decoding circuit after the second data is read from the recording medium.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 2, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syosuke Maruyama, Kana Furuhashi
  • Publication number: 20190096471
    Abstract: According to one embodiment, semiconductor memory device includes a first circuit that determines data stored in a memory cell; and a second circuit that controls the first circuit, wherein in a sequence in which the second circuit writes first data in the memory cell, the first circuit generates a first current of a first current value, and determines data stored in the memory cell based on the first current and a second current flowing in the memory cell, and in a sequence in which the second circuit writes second data different from the first data in the memory cell, the first circuit generates a third current of a second current value different from the first current value, and determines data stored in the memory cell based on the third current and the second current.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 28, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Toshiaki DOZAKA
  • Patent number: 10241531
    Abstract: According to an embodiment of the present invention, a power supply device includes a switching circuit, a detection circuit, a first comparator, a current source circuit, and a delay circuit. The switching circuit performs switching control of a power supply voltage. The detection circuit detects an output voltage from the switching circuit. The first comparator compares the voltage detected by the detection circuit with a first reference voltage which is set in advance. The current source circuit outputs a bias current which has correlation with the power supply voltage. The delay circuit receives the bias current from the current source circuit, and outputs, to the switching circuit, a delay time which corresponds to an increase time of the output voltage, by using the bias current in accordance with the result of comparison performed by the first comparator.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 26, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tatsuhiko Maruyama
  • Patent number: 10242708
    Abstract: A disk apparatus includes a disk, a head, a circuit board, and an abnormality detection circuit. The head includes a plurality of loads, including at least a first load and a second load, associated with writing or reading of data to or from the disk, and a plurality of head terminals corresponding to and connected to the plurality of loads, respectively. The circuit board includes board terminals corresponding to and connected to the plurality of head terminals, respectively, and a preamplifier that applies a voltage to the loads via the plurality of board terminals during writing or reading of the data to or from the disk. The abnormality detection circuit detects a short-circuit between a first board terminal, which is the board terminal connected to the head terminal of the first load, and a second board terminal, which is the board terminal connected to the head terminal of the second load.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 26, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Nobuyoshi Yamasaki
  • Publication number: 20190088648
    Abstract: A semiconductor device is provided having a first region and a second region surrounding the first region includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type between the first electrode and the second electrode, a second semiconductor layer of the first conductivity type located over the first semiconductor layer, a third semiconductor layer of the second conductivity type on the second semiconductor layer in the first region, a fourth semiconductor layer of the first conductivity type between the third semiconductor layer and the second semiconductor layer, a fifth semiconductor layer of the second conductivity type on the second semiconductor layer in the second region, and a sixth semiconductor layer of the first conductivity type located between the fifth semiconductor layer and the second semiconductor layer, wherein the width of the fourth semiconductor layer is less than the width of the sixth semiconductor layer.
    Type: Application
    Filed: March 5, 2018
    Publication date: March 21, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yoichi HORI