Patents Assigned to TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
  • Patent number: 11363595
    Abstract: A wireless communication apparatus which can simultaneously conduct communication on at least two frequency channels is described. The apparatus includes a communication unit which refers to a connection management table to determine a communication system which can be used by a wireless communication terminal using an identifier of the wireless communication terminal, and conducts communication with the wireless communication terminal on a second frequency channel using the communication system, when a request from the wireless communication terminal to change the first frequency channel to the second frequency channel is permitted.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 14, 2022
    Assignee: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoko Adachi, Toshihisa Nabetani, Kiyoshi Toshimitsu, Tatsuma Hirano
  • Patent number: 11356154
    Abstract: According to one embodiment, a wireless communication device includes: a receiver configured to receive a plurality of first frames each including first information required for uplink multi-user transmission; and a transmitter configured to transmit a second frame generated on the basis of the first information included in the plurality of first frames. The transmitter does not transmit a transmission request for the first information before the first frames are received. The second frame is a frame instructing transmission of a third frame including data after a predetermined time from reception of the second frame.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: June 7, 2022
    Assignee: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tomoko Adachi
  • Patent number: 11327718
    Abstract: An arithmetic circuitry includes a first processing circuitry, a second processing circuitry, an adder circuitry, and a saturation logic circuitry. The first processing circuitry divides one input term into blocks each of which being divided for each predetermined digit number, to make a least significant bit of each of the blocks overlap with a most significant bit of the adjacent and low-order block, and calculates a partial product of each of the blocks and the other input term based on Booth recoding in which a sign is controlled when Booth recoding values become ±0. The second processing circuitry simplifies the partial products. The adder circuitry outputs the sum of a result obtained through the simplification and an addition term. The saturation logic circuitry executes saturation processing based on a result outputted by the second processing circuitry and a result outputted by the adder circuitry.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 10, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tatsuya Namatame
  • Patent number: 11327893
    Abstract: According to one embodiment, an electronic device includes an interface configured to carry out communication according to a predetermined protocol, and a control section configured to add a response frame to a response to a command to be received through the interface, and transmit the response to which the response frame is added through the interface. The control section includes a setting section configured to set an arbitrarily settable field included in the response frame to a plurality of sections.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: May 10, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masashi Shimoda
  • Patent number: 11327829
    Abstract: A semiconductor device of an embodiment includes a main circuit configured to perform a predetermined operation to an input signal to output an output signal, an inverse operation circuit configured to receive the output signal of the main circuit as an input, and perform an inverse operation of the predetermined operation by using the output signal to output an inverse operation result signal, and a comparison circuit configured to compare the input signal and the inverse operation result signal, and output a predetermined signal when the input signal and the inverse operation result signal do not coincide with each other.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 10, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Shigeru Nakajima
  • Patent number: 11329473
    Abstract: According to one aspect of embodiments, a driver circuit having an overcurrent protection function includes a control signal generating circuit that outputs a Pulse Width Modulation (PWM) control signal for controlling turning ON and OFF of the output transistor that supplies output current to a load; and a control circuit that generates a signal indicating an overcurrent state when a count value of an overcurrent detecting signal exceeds a predetermined number, which indicates that a value of an output current of the output transistor within the predetermined time interval exceeds a predetermined threshold value.
    Type: Grant
    Filed: July 19, 2020
    Date of Patent: May 10, 2022
    Assignees: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, AISIN AW CO., LTD.
    Inventors: Hiroyuki Sugiyama, Yuji Yamanaka, Tatsufumi Kurokawa
  • Publication number: 20220140120
    Abstract: According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor member, and first and second insulating members. The semiconductor member is located between the second and first electrodes, and includes a first semiconductor region a second semiconductor region between the first semiconductor region and the first electrode, a third semiconductor region between the second semiconductor region and the first electrode, a fourth semiconductor region between the second semiconductor region and the first electrode, a fifth semiconductor region between the first semiconductor region and the second electrode, a sixth semiconductor region between the fifth semiconductor region and the second electrode, and a seventh semiconductor region between the fifth semiconductor region and the second electrode. A portion of the first insulating member is between the third electrode and the semiconductor member.
    Type: Application
    Filed: August 25, 2021
    Publication date: May 5, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Ryohei GEJO, Tatsunori SAKANO, Takahiro KATO
  • Publication number: 20220140865
    Abstract: According to one embodiment, there is provided a magnetic coupling device including a first coil, a second coil, a third coil, a fourth coil, a first constant-potential node and a second constant-potential node. The second coil is electrically connected with one end of the first coil and wound in a direction opposite to a direction in which the first coil is wound. The third coil faces the first coil. The fourth coil faces the second coil. The first constant-potential node is electrically connected with one end of the third coil. The second constant-potential node is electrically connected with one end of the fourth coil.
    Type: Application
    Filed: January 10, 2022
    Publication date: May 5, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toyoaki UO, Tsuneo SUZUKI, Hiroaki ISHIHARA
  • Publication number: 20220140137
    Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer including a first plane extending along a plane including a first axis and a second axis; a first electrode extending along the first axis; a second electrode extending along the second axis; and a third electrode above the first plane. The third electrode is electrically coupled to the first electrode and the second electrode, and includes a first portion, a second portion and a third portion. The first portion crosses the first electrode. The second portion crosses the second electrode. The third portion crosses the second electrode and is separate at a first end from the second portion.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 5, 2022
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kentaro ICHINOSEKI, Tatsuya Nishiwaki, Kikuo Aida, Kohei Oasa
  • Publication number: 20220140731
    Abstract: A semiconductor device according to embodiments includes a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first element having a first end portion electrically connected to the first control electrode and a second end portion electrically connected to the first electrode, and the first element including a first capacitance component; and, a second element having a third end portion electrically connected to the first control electrode and the first end portion and a fourth end portion, and the second element including a second capacitance component, wherein, when a threshold voltage of the normally-off transistor is denoted by Vth, a maximum rated gate voltage of the normally-off transistor is denoted by Vg_max, a voltage of the fourth end portion is denoted by Vg_on, the first capacitance component is deno
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira YOSHIOKA, Toru SUGIYAMA, Masaaki IWAI, Naonori HOSOKAWA, Masaaki ONOMURA, Hung HUNG, Yasuhiro ISOBE
  • Patent number: 11322608
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer provided on a portion of the first semiconductor layer, a third semiconductor layer provided on a portion of the second semiconductor layer and separated from the first semiconductor layer, a fourth semiconductor layer provided on an other portion of the first semiconductor layer, a first insulating film provided on a portion between the third semiconductor layer and the fourth semiconductor layer and on a portion of the fourth semiconductor layer at the second semiconductor layer side, a second insulating film contacting the first insulating film, a third insulating film provided above the second insulating film, and an electrode provided on the first insulating film, on the second insulating film, and on the third insulating film. The second insulating film is provided on the fourth semiconductor layer, and is thicker than the first insulating film.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yasunori Iwatsu
  • Patent number: 11320464
    Abstract: A chip package according to one embodiment includes a magnetic field sensor and a chip housing. The chip housing is a rectangular parallelepiped body. A solenoid coil is wound around four outer surfaces of the chip housing. The magnetic field sensor is disposed in the chip package. A plurality of first electrode pads connected to the solenoid coil and a plurality of second electrode pads connected to the magnetic field sensor are disposed on one mounting surface.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Jia Liu
  • Patent number: 11322181
    Abstract: According to one embodiment, a magnetic disk device includes a disk, a head including a write head and a first read head and a second read head, and a controller that disposes the first read head at a first radial position of a first track of the disk in a radial direction to read the first track, changes a main read head which serves as a reference for positioning during a read process from the first read head to the second read head when read retrying the first track, disposes the second read head as the main read head at a second radial position different from the first radial position of the first track in the radial direction to read the first track, and changes an internal setting corresponding to the main read head to read the first track.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Nobuhiro Maeto
  • Patent number: 11320463
    Abstract: A current detection device includes a first coil, a magnetic field detection element, a shield layer, a second coil, and an operation circuit. The first coil has a planar shape. The magnetic field detection element is disposed in a spaced apart manner from the first coil in a direction orthogonal to a plane of the first coil, and is disposed so as to receive a magnetic field which the first coil generates. The shield layer is disposed between the first coil and the magnetic field detection element. The second coil is disposed in a spaced apart manner from the first coil with respect to an axis perpendicular to the shield layer. The operation circuit operates the second coil.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Jia Liu
  • Patent number: 11322585
    Abstract: A semiconductor device includes a semiconductor layer. The semiconductor layer has bottom and upper surfaces opposite to each other in a first direction. The semiconductor layer includes a first region of a first conductivity type at the bottom surface, a second region of the first conductivity type at the bottom surface surrounding the first region, a third region of the first conductivity type above the first and second regions, and a fourth region of a second conductivity type extending from the upper surface into the third region. In a first cross sectional plane along the first direction, an outer edge of the first region is within an outer edge of the fourth region by a first distance. In a second cross sectional plane along the first direction, an outer edge of the first region is within an outer edge of the fourth region by a second distance.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Shoko Hanagata
  • Patent number: 11322581
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first and fourth semiconductor regions of a first conductivity type, and second and third semiconductor regions of a second conductivity type. The third semiconductor region is provided around the second semiconductor region along a first plane crossing a first direction from the first electrode toward the first semiconductor region and is separated from the second semiconductor region. The fourth semiconductor region is provided around the third semiconductor region along the first plane, and has a greater impurity concentration of the first conductivity type than the first semiconductor region. The second electrode is provided on the second semiconductor region and is electrically connected to the second semiconductor region.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Patent number: 11321131
    Abstract: According to one embodiment, an evaluation device includes one or more processors. The one or more processors performs detecting a process of activating a hardware of a system LSI from an application, interrupting execution of the application when the process of activating the hardware is detected, setting, as a load, a memory access pattern of the hardware estimated by simulating performance of the hardware, adding the load to resume the execution of the application, and collecting a profile related to a memory access during the execution of the application, including the load when the execution of the application is resumed.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yuji Ishikawa
  • Patent number: 11322612
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kentaro Ichinoseki, Tatsuya Nishiwaki, Shingo Sato
  • Patent number: 11313956
    Abstract: A photodetector includes a plurality of first light detection elements having a first driving voltage range, the first light detection elements including first semiconductor layers having a first conductivity type and second semiconductor layers having a second conductivity type different from the first conductivity type; and a second light detection element having a second driving voltage range different from the first driving voltage range, the second light detection element including a third semiconductor layer having the first conductivity type and a fourth semiconductor layer having the second conductivity type.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 26, 2022
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Honam Kwon, Ikuo Fujiwara, Kazuhiro Suzuki, Keita Sasaki, Yuki Nobusa
  • Patent number: 11317300
    Abstract: According to one embodiment, a wireless communication device, includes a receiver configured to receive a first field, receive at least one of a plurality of second fields having been multiplexed and transmitted, and decode the one of the second fields to obtain a frame in a case where first information identifying the wireless communication device is not set in the first field, and a controller configured to suppress access to a wireless medium during a period indicated by a value set in the frame.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 26, 2022
    Assignee: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoko Adachi, Ryoko Matsuo, Tomoya Tandai, Hiroki Mori, Kentaro Taniguchi