Patents Assigned to Townsend and Townsend and Crew
  • Patent number: 5713005
    Abstract: A method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input. The data associated with the read cycle propagates asynchronously through the memory to produce data which is then input to the pipeline circuit. The apparatus includes steering circuitry with precise timing for steering the data produced in the read cycle into an asserted one of several branches of a register. Selection circuitry is used to select for output the data which has been stored in the asserted branch upon receipt of a subsequent clock. The subsequent clock is one which occurs a programmable number of clocks after the first clock.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: January 27, 1998
    Assignee: Townsend and Townsend and Crew LLP
    Inventor: Robert J. Proebsting
  • Patent number: 5689462
    Abstract: A memory circuit with programmable memory array organization and number of data output terminals, capable of connecting unused output buffers in parallel in organizations requiring fewer output terminals than the maximum possible. Parallel connection of output buffers improves output transient performance and employs otherwise dfsabled output buffers to reduce waste of silicon area.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: November 18, 1997
    Assignee: Townsend and Townsend and Crew, LLP
    Inventor: Robert J. Proebsting
  • Patent number: 5495445
    Abstract: A redundancy scheme for memory circuits that eliminates the need for physical disconnection or logical deselection of defective elements. The invention does not require disabling a defective element and allows it to operate and generate bad data. The circuit is designed such that the redundant element is able to override the defective element. Various approaches to row and column redundancy based on this principal are disclosed for memory circuit such as dynamic and static random access memories.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: February 27, 1996
    Assignee: Townsend and Townsend and Crew
    Inventor: Robert J. Proebsting