Patents Assigned to Ultratech, Inc.
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Publication number: 20140151344Abstract: A movable microchamber system with a gas curtain is disclosed. The microchamber system has a top member with a light-access feature and a stage assembly that supports a substrate to be processed. The stage assembly is disposed relative to the top member to define a microchamber and a peripheral microchamber gap. An inert gas is flowed into the peripheral microchamber gap to form the gas curtain just outside of the microchamber. The gas curtain substantially prevents reactive gas in the ambient environment from entering the microchamber when the stage assembly moves relative to the top member.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: Ultratech, Inc.Inventors: Digby PUN, Ali SHAJII, Andrew B. COWE, Raymond ELLIS, James T. McWHIRTER
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Apparatus and method for improving the intensity profile of a beam image used to process a substrate
Patent number: 8742286Abstract: Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to form an image having an intensity profile with an extended uniform region useful for thermally processing the surface of the substrate. The image may be scanned across the surface to heat at least a portion of the substrate surface to achieve a desired temperature within a predetermined dwell time. Such processing may achieve a high efficiency due to the large proportion of energy contained in the uniform portion of the beam.Type: GrantFiled: January 19, 2012Date of Patent: June 3, 2014Assignee: Ultratech, Inc.Inventors: Andrew M Hawryluk, Boris Grek, David A Markle -
Patent number: 8735251Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.Type: GrantFiled: October 4, 2013Date of Patent: May 27, 2014Assignee: Ultratech, Inc.Inventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Patent number: 8691598Abstract: Systems and methods for performing semiconductor laser annealing using dual loop control are disclosed. The first control loop operates at a first frequency and controls the output of the laser and controls the 1/f laser noise. The second control loop also controls the amount of output power in the laser and operates at second frequency lower than the first frequency. The second control loop measures the thermal emission of the wafer over an area the size of one or more die so that within-die emissivity variations are average out when determining the measured annealing temperature. The measured annealing temperature and an annealing temperature set point are used to generate the control signal for the second control loop.Type: GrantFiled: December 6, 2012Date of Patent: April 8, 2014Assignee: Ultratech, Inc.Inventors: James T. McWhirter, David Gaines, Joseph Lee, Paolo Zambon
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Publication number: 20140094007Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.Type: ApplicationFiled: October 4, 2013Publication date: April 3, 2014Applicant: Ultratech, Inc.Inventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Patent number: 8669660Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.Type: GrantFiled: December 20, 2012Date of Patent: March 11, 2014Assignee: Ultratech, Inc.Inventors: Timothy H. Daubenspeck, Timothy D. Sullivan
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Patent number: 8658451Abstract: Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.Type: GrantFiled: July 20, 2011Date of Patent: February 25, 2014Assignee: Ultratech, Inc.Inventors: Yun Wang, Andrew M. Hawryluk
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Patent number: 8643190Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.Type: GrantFiled: November 29, 2010Date of Patent: February 4, 2014Assignee: Ultratech, Inc.Inventors: Edward Crandal Cooney, III, Peter James Lindgren, Doreen Jane Ossenkop, Anthony Kendall Stamper
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Patent number: 8637937Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.Type: GrantFiled: February 2, 2012Date of Patent: January 28, 2014Assignee: Ultratech, Inc.Inventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Publication number: 20130330844Abstract: Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 ?s to about 100 ?s. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed.Type: ApplicationFiled: June 4, 2013Publication date: December 12, 2013Applicant: Ultratech, Inc.Inventors: Andrew M. Hawryluk, Serguei Anikitchev
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Publication number: 20130321935Abstract: A unit magnification Wynn-Dyson lens for microlithography has an image field sized to accommodate between four and six die of dimensions 26 mm×36 mm. The lens has a positive lens group that consists of either three or four refractive lens elements, with one of the lens elements being most mirror-wise and having a prism-wise concave aspheric surface. Protective windows respectively reside between object and image planes and the corresponding prism faces. The lens is corrected for at least the i-line LED wavelength spectrum or similar LED-generated wavelengths.Type: ApplicationFiled: May 20, 2013Publication date: December 5, 2013Applicant: Ultratech, Inc.Inventor: David G. Stites
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Patent number: 8592309Abstract: Methods of performing laser spike annealing (LSA) in forming gallium nitride (GaN) light-emitting diodes (LEDs) as well as GaN LEDs formed using LSA are disclosed. An exemplary method includes forming atop a substrate a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method also includes performing LSA by scanning a laser beam over the p-GaN layer. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.Type: GrantFiled: November 6, 2009Date of Patent: November 26, 2013Assignee: Ultratech, Inc.Inventors: Yun Wang, Andrew M. Hawryluk
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Patent number: 8580673Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.Type: GrantFiled: January 8, 2013Date of Patent: November 12, 2013Assignee: Ultratech, Inc.Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Marie-Claude Paquet, Wolfgang Sauter, Timothy D. Sullivan
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Publication number: 20130278109Abstract: A betavoltaic power source for mobile devices and mobile applications includes a stacked configuration of isotope layers and energy conversion layers. The isotope layers have a half-life of between about 0.5 years and about 5 years and generate radiation with energy in the range from about 15 keV to about 200 keV. The betavoltaic power source is configured to provide sufficient power to operate the mobile device over its useful lifetime.Type: ApplicationFiled: April 15, 2013Publication date: October 24, 2013Applicant: Ultratech, Inc.Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk
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Patent number: 8546805Abstract: Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings the wafer surface temperature up to the annealing temperature. The anneal laser beam can have a different wavelength, or the same wavelength but different orientation relative to the wafer surface. Reflectivity maps of the wafer surface at the preheat and anneal wavelengths are measured and used to select first and second intensities that ensure good anneal temperature uniformity as a function of wafer position.Type: GrantFiled: January 27, 2012Date of Patent: October 1, 2013Assignee: Ultratech, Inc.Inventors: Xiaohua Shen, Yun Wang, Xiaoru Wang
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Patent number: 8541291Abstract: An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.Type: GrantFiled: June 14, 2011Date of Patent: September 24, 2013Assignee: Ultratech, Inc.Inventors: Bruce K. Furman, Jae-Woong Nah
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Patent number: 8541299Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.Type: GrantFiled: May 26, 2010Date of Patent: September 24, 2013Assignee: Ultratech, Inc.Inventors: Stephen Leslie Buchwalter, Bruce K. Furman, Peter A. Gruber, Jae-Woong Nah, Da-Yuan Shih
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Patent number: 8501638Abstract: Laser annealing scanning methods that result in reduced annealing non-uniformities in semiconductor device structures under fabrication are disclosed. The methods include defining a length of an annealing laser beam such that the tails of the laser beam resided only within scribe lines that separate the semiconductor device structures. The annealing laser beam tails from adjacent scan path segments can overlap or not overlap within the scribe lines. The cross-scan length of the annealing laser beam can be selected to simultaneously scan more than one semiconductor device structure, as long as annealing laser beam is configured such that the tails do not fall within a semiconductor device structure.Type: GrantFiled: April 27, 2012Date of Patent: August 6, 2013Assignee: Ultratech, Inc.Inventor: Arthur W. Zafiropoulo
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Patent number: 8461695Abstract: Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature.Type: GrantFiled: January 24, 2012Date of Patent: June 11, 2013Assignee: Ultratech, Inc.Inventor: Mukta G. Farooq
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Patent number: 8460959Abstract: Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing having a time duration of 10 seconds or faster. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.Type: GrantFiled: August 24, 2011Date of Patent: June 11, 2013Assignee: Ultratech, Inc.Inventors: Yun Wang, Andrew M. Hawryluk