Patents Assigned to United Microelectronics Corporation
  • Patent number: 9496251
    Abstract: The present invention provides electrostatic discharge protectors. One aspect of the present invention provides an electrostatic discharge protector includes a substrate, an electrostatic discharge protection circuit disposed on the substrate, and a pickup ring surrounding the electrostatic discharge protection circuit. The pickup ring has a plurality of low resistance zones where a doping layer, a contact and a metal layer are connected in sequence, and the low resistance zones are distributed within the pickup ring separately and unequally.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 15, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Lu-An Chen, Mei-Ling Chao, Tien-Hao Tang
  • Patent number: 9496390
    Abstract: A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region. The substrate has at least one protruding portion. The first source having a first conductivity type is formed on the substrate. The drain having the first conductivity type is disposed on the protruding portion. The first gate electrode is disposed adjacent to a first sidewall of the protruding portion. The first gate dielectric layer is disposed between the first gate electrode and the first sidewall as well as being disposed adjacent to the first source and the drain. The first doping region having a second conductivity type is formed beneath the protruding portion and adjacent to the first source.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: November 15, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hao Su, Hang Hu, Hong Liao
  • Patent number: 9494873
    Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 15, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: En-Chiuan Liou, Teng-Chin Kuo, Yuan-Chi Pai, Chun-Chi Yu
  • Patent number: 9490141
    Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: November 8, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Wei-Nan Fang, Jiann-Shiun Chen, Tzu-Yi Chuang
  • Patent number: 9478457
    Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 25, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Ming-Shing Chen, Yu-Ting Wang, Ming-Hui Chang
  • Patent number: 9466497
    Abstract: The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Hsiang-Chen Lee, Yu-Chun Chang, Chia-Wen Wang, Meng-Chun Chen, Chih-Yang Hsu
  • Publication number: 20160276215
    Abstract: A method for manufacturing a semiconductor device is provided. The method comprises steps as follows. At least one trench is provided in a low-k dielectric layer on a substrate. The trench is filled with a copper (Cu) film. Pure cobalt (Co) is deposited on a surface of the Cu film by introducing a flow of a carrier gas carrying a Co-containing precursor and a reducing agent onto the surface of the Cu film. The flowrate of the flow is within a range from 5 to 19 sccm.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 22, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: PEI-TING LEE, GUO-WEI CHEN, CHUN-LING LIN, CHI-MAO HSU, CHING-WEI HSU, HUEI-RU TSAI, JIA-RONG LI, SHANG NAN CHOU, PO CHIH WU
  • Patent number: 9443970
    Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hsin-Ming Hou, Yu-Cheng Tung, Ji-Fu Kung, Wai-Yi Lien, Ming-Tsung Chen
  • Patent number: 9443902
    Abstract: A fabricating method of a back-illuminated image sensor includes the following steps. First, a silicon wafer having a first surface and a second surface is provided, wherein a number of trench isolations are formed in the first surface, and at least one image sensing member is formed between the trench isolations. Then, a first chemical mechanical polishing (CMP) process is performed to the second surface using the trench isolations as a polishing stop layer to thin the silicon wafer. Because the polishing rate of the silicon material in the silicon wafer is different with that of the isolation material of the trench isolations in the first CMP process, at least one dishing depression is formed in the second surface of the silicon wafer. Finally, a microlens is formed above the dishing depression, and a surface of the microlens facing the dishing depression is a curved surface.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Tseng-Fei Wen
  • Publication number: 20160260820
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: JHEN-CYUAN LI, SHUI-YEN LU, MAN-LING LU, YU-CHENG TUNG, CHUNG-FU CHANG
  • Patent number: 9401441
    Abstract: A fabricating method of a back-illuminated image sensor includes the following steps. First, a silicon wafer having a first surface and a second surface is provided, wherein a number of trench isolations are formed in the first surface, and at least one image sensing member is formed between the trench isolations. Then, a first chemical mechanical polishing (CMP) process is performed to the second surface using the trench isolations as a polishing stop layer to thin the silicon wafer. Because the polishing rate of the silicon material in the silicon wafer is different with that of the isolation material of the trench isolations in the first CMP process, at least one dishing depression is formed in the second surface of the silicon wafer. Finally, a microlens is formed above the dishing depression, and a surface of the microlens facing the dishing depression is a curved surface.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: July 26, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Tseng-Fei Wen
  • Patent number: 9391197
    Abstract: A semiconductor device includes a substrate; a deep well region disposed in the substrate; an element region disposed in the substrate and in the deep well region; a drain region disposed in the substrate, in the deep well region, and surrounding the element region; a gate structure disposed on the surface of the substrate, adjacent to the deep well region, and surrounding the drain region; a well region disposed in the substrate, in the deep well region, and surrounding the gate structure; a source region disposed in the substrate, in the well region, and surrounding the gate structure; a body contact region disposed separately from the source region in the well region and surrounding the source region; and an annular doped region disposed separately from the deep well region in the substrate and surrounding the deep well region.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: July 12, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shih Chieh Pu, Ming-Tsung Lee, Cheng-Hua Yang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 9391177
    Abstract: The present invention provides a method for improving gate coupling ratio of a flash memory device and a protruding floating gate is formed. First, a substrate having a plurality of isolation structures is formed. Then, a first conductive layer is formed overlaying the substrate. A chemical-mechanical polishing process is performed to planarize the first conductive layer. After that, a portion of the isolation structures is removed, and a second conductive layer is formed overlaying the first conductive layer and the isolation structures. Finally, a lithography process with a photomask can be used to define a mask that covers the first conductive layer and the second conductive layer, and then an insulating layer is deposited overlaying the substrate, so that a third conductive layer is formed overlaying the insulating layer.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 12, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chu-Ming Ma, Chun-Yi Lin, Hung-Chi Huang, Hsien-Ta Chung
  • Patent number: 9385191
    Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Patent number: 9378968
    Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yi-Ching Wu, Horng-Bor Lu, Yung-Chieh Kuo
  • Patent number: 9378958
    Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang
  • Patent number: 9373718
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: June 21, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Jhen-Cyuan Li, Shui-Yen Lu, Man-Ling Lu, Yu-Cheng Tung, Chung-Fu Chang
  • Patent number: 9373705
    Abstract: The present invention provides a manufacturing method of a fin-shaped field effect transistor (FinFET), comprises the following steps. Firstly, providing a substrate having a fin structure; forming a gate structure on the fin structure perpendicular to a extending direction of the fin structure; performing an amorphous implantation to form an amorphous layer on a exposed portion of the fin structure exposed by the gate structure and a light-doping implantation; forming a sacrificial spacer on sides of the gate structure covering a portion of the amorphous layer on the fin structure; forming a trench on the fin structure adjacent to the sacrificial spacer; growing an alloy in the trench; and then removing the sacrificial spacer. The invention also provides a FinFET device thereof.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: June 21, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chun-Yu Chen, Chung-Ting Huang, Ming-Hua Chang, Tien-Chen Chan, Yen-Hsing Chen, Hsin-Chang Wu
  • Publication number: 20160163837
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YEN-LIANG WU, CHUNG-FU CHANG, YU-HSIANG HUNG, SSU-I FU, WEN-JIUN SHEN, MAN-LING LU, CHIA-JONG LIU, YI-WEI CHEN
  • Patent number: 9362358
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: June 7, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo