Abstract: An off-line controller circuit having a line voltage detector and a switched current bootstrap circuit. The controller receives current from the line and provides a drive signal for controlling the switch(es) of an off-line converter. The line voltage detector establishes a voltage proportional to the line voltage in response to a portion of the received line current. The proportional voltage is compared to a reference voltage to provide a control signal for inhibiting the drive signal when the proportional voltage is less than the reference voltage, indicating that the line voltage is less than a predetermined level. The switched current bootstrap circuit limits a bootstrap current provided to the controller supply voltage from the converter output in accordance with current shunted to ground by a supply voltage clamp.

Abstract: A controllable bus terminator for providing a switchable termination on a bus having a plurality of conductors, wherein the controllable bus terminator includes a voltage regulator, a plurality of termination networks, each having a first terminal and a second terminal wherein the second terminal of each of the termination networks provides an output terminal of the bus terminator. The bus terminator further includes a plurality of electrically controllable switches, each of the switches having a first port coupled to the voltage regulator and a second port coupled to the first terminal of a corresponding one of the termination networks wherein each of the switches couples the corresponding termination network to the voltage regulator when the corresponding switch is in a first state and wherein each of the switches disconnects the corresponding termination network from the voltage regulator when the corresponding switch is in a second state.

Abstract: An adaptive battery charger circuit including a state machine adjusts the charging current in accordance with the battery charge acceptance. The battery charging cycle includes an initial charging phase characterized by a relatively high charge acceptance, an intermediate charging phase characterized by a decreasing charge acceptance and a rising battery temperature, and a final charging phase characterized by the battery being at substantially full charge and the charge acceptance approaching zero. Each charging phase corresponds to one or more states of the state machine. Multiple sets of conditions causing transitions between the states of operation are derived from a model of a battery under charge which relates charge acceptance, battery temperature, and cumulative supplied charge. During the intermediate charging phase, the charging current is adjusted to maintain a predetermined battery temperature for a predetermined duration.

Abstract: An inverter circuit having a readily programmable and stable threshold voltage and low propagation delay. An input stage of the inverter includes a pair of transistors, a first one adapted to receive an input signal for inversion and being disposed in a first current path and a second one being disposed in a second current path. The input stage further comprises a third transistor connected in series with the first transistor and receiving a bias voltage. The first, second, and third transistors are all of the same type; i.e., all NMOS or all PMOS. An output stage of the inverter includes a PMOS transistor and an NMOS transistor having interconnected drain terminals at which an inverted output signal is provided. The threshold voltage about which the output signal transitions is a function of the bias voltage and characteristics of the first, second, and third transistors in the input stage.

Abstract: A bandgap reference voltage circuit adapted for low current applications. A reference voltage is provided as a function of the difference between the V.sub.be voltages of a pair of bipolar transistors scaled by a ratio of the resistances of a pair of MOS transistors, to provide a predetermined reference voltage level. For a given reference voltage circuit size, use of the pair of MOS transistors achieves a low reference current in an integrated circuit, the size of which is far less than that implemented with conventional resistors. Alternatively, for a given reference current, the MOS transistor scaling provides a smaller reference circuit than is otherwise achievable.

Abstract: A switching regulator having improved dynamic response to load variations includes a load compensation circuit coupled to the output terminal. The load compensation circuit supplies current to a load coupled to the output terminal when the output voltage is less than a first predetermined level and/or diverts current away from the load when the output voltage is greater than a second predetermined level. The load compensation circuit operates in this manner until the output voltage is between the first and second predetermined levels. The load compensation circuit responds faster to load variations than the switching regulator to accommodate sudden changes in the load demand.

Abstract: A semiconductor device is disclosed having improved vertical gain symmetry, and which includes thick, lightly-doped regions which are dielectrically isolated and provided by at least two separately processed semiconductor wafers which are bonded together and further processed to provide the finished device. Alternate embodiments include buried layers exhibiting very low resistance. Further alternate embodiments provide high voltage and/or high current devices which are fabricated together with low-power circuitry as an integrated circuit.

Abstract: A pulse width modulator voltage feedforward circuit which includes a gating circuit for providing a control signal to a charge circuit which charges an integration circuit with a current proportional to an input voltage. The integration circuit provides an output ramp signal waveform having a slope proportional to the input voltage value. The gating circuit also provide a control signal to a discharge circuit, to thus alternately charge and discharge the integration circuit. The gating circuit insures that a minimum deadtime for a transformer reset will occur regardless of input voltage variations by preventing a fixed frequency signal provided by an oscillator from beginning a new ramp waveform signal period until the integration circuit is discharged to a minimum reference voltage level.

Abstract: A bus terminator, for a computer bus, which is capable of providing maximum allowable current to the bus, voltage clamping of the bus and steady state power reduction when the bus is in the positive steady state.

Abstract: An improved push-pull amplifier having a driver circuit for driving a source follower output transistor. The driver circuit includes a replicating transistor having electrical characteristics substantially similar to those of the source follower transistor, a buffer amplifier, and a circuit, coupled to the replicating transistor and the buffer amplifier, for summing the voltage across the replicating transistor and the buffer output signal to provide a gate signal to the source follower output transistor. A cross current feedback circuit regulates the quiescent current flow through the output transistors by adjusting the gate signal provided to the upper, source follower output transistor in response to a sensed current flow through the lower output transistor.

Abstract: A high power factor regulator circuit which includes a variable multiplier, permitting the high power factor regulator circuit to be used with a number of input line voltage levels. In one embodiment a comparator determines the multiplication or gain factor to be applied in a control loop by comparing the rectified AC input voltage to a predetermined threshold value.

Abstract: A controllable bus terminator for providing a switchable termination on a bus having a plurality of conductors, wherein the controllable bus terminator includes a voltage regulator, a plurality of termination networks, each having a first terminal and a second terminal wherein the second terminal of each of the termination networks provides an output terminal of the bus terminator. The bus terminator further includes a plurality of electrically controllable switches, each of the switches having a first port coupled to the voltage regulator and a second port coupled to the first terminal of a corresponding one of the termination networks wherein each of the switches couples the corresponding termination network to the voltage regulator when the corresponding switch is in a first state and wherein each of the switches disconnects the corresponding termination network from the voltage regulator when the corresponding switch is in a second state.

Abstract: An active negation emulator circuit for improving the noise margin of signals carried by a signal interface bus. The circuit includes a sensor for sensing the voltage on the bus and a variable current source for supplying a current to the bus when the voltage level thereon is greater than a predetermined value. More particularly, when the voltage level on the bus is indicative of the signal carried thereby being in a logic high state, a current is supplied to raise the voltage level to the desired logic high voltage level. A combination circuit is also provided including an active negation emulator circuit, a resistive terminator, and switch means for selectively coupling the active negation emulator to the signal interface bus, coupling the resistive terminator to the signal interface bus, or decoupling both the emulator and the terminator from the bus, in accordance with the location of the bus to which the combination circuit is coupled.

Abstract: A controller for controlling a resonant switching dc to dc converter. The controller has four output terminals, each of which is capable of switching one of four transistors in a bridge power stage in such a way as to accomplish zero-voltage resonant switching. The phase relationship between the switching of the four transistors of the bridge power stage which is adjustable from approximately zero to 180.degree., results in highly-efficient, pulse-width-modulation of the output power.

Abstract: A controllable bus terminator, for providing a switchable termination on a bus having a plurality of conductors, wherein the controllable bus terminator includes a voltage regulator, a plurality of resistive networks each of the resistive networks having a first terminal and a second terminal wherein the second terminal of each of the resistive networks provides an output terminal of the bus terminator. The bus terminator further includes a plurality of electrically controllable switches, each of the switches having a first port coupled to the voltage regulator and a second port coupled to the first terminal of a corresponding one of the resistive networks wherein each of the switches couple the corresponding resistive network to the voltage regulator when the corresponding switch is in a first state and wherein each of the switches disconnect the corresponding resistive network from the voltage regulator when the corresponding switch is in a second state.

Abstract: Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the "on" time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible.

Abstract: A molded package with a leadframe locking structure is shown. A lower leadframe consists of a frame member, a connecting element extending therefrom, a mounting member at the distal end of the connecting element, and at least one side element projecting from the mounting member. Electrical connection is made between the mounting member and a semiconductor device. An upper leadframe consists of a frame member and an extending lead element which makes electrical contact with an upper surface of the semiconductor device. There is at least one side element bent up to a predetermined angle relative to the mounting member so that an encapsulant will be locked in place, minimizing the possibility of semiconductor contamination via boundaries between the encapsulant and the leadframes. The encapsulant, such as plastic or epoxy, is transfer or injection molded over the lead element, over the semiconductor device, about the side element, and on top of the mounting member to form the completed package.

Abstract: A silicon controlled rectifier device including an SCR portion controlled by an input voltage signal to a voltage comparator and having a latching circuit to permit the SCR portion to remain in the conducting state once switched even in the absence of the input voltage signal. Such a device is especially useful when a narrow input voltage signal is used to switch the SC portion into its conducting state.

Abstract: A low-voltage CMOS switching controller which utilizes PMOS and nMOS devices to control the switching of a high voltage power supply. Two pMOS devices are used as switches to control the high voltage level on an output terminal and an nMOS device is used to switch the output terminal to ground once the high voltage has been reduced to a safe level. The controller also includes circuitry which prevents both pMOS devices from being on at the same time, thereby shunting the high voltage supply to ground.

Abstract: A transformer isolated circuit for driving a semiconductor power switch includes a transformer which is driven with a high frequency Pulse Width Modulated (PWM) signal in such a way that the constantly present PWM carrier supplies the power needed for high gate current pulses, while different duty cycles determine the "on" or "off" state of the power device under control. Transformer saturation is prevented by sensing primary current and returning it to zero once per PWM cycle. Because of the high PWM carrier frequency used, the average transformer power is low, yet the secondary side is able to deliver high pulse currents for fast "on-off" switching of the gate of even the largest N- or P-channel device, without need for auxiliary power supplies. Also included are provisions for extremely fast output current limiting, for use where short circuit protection is necessary. Discussion of a monolithic implementation is included.