Abstract: A method for fabricating a buried zener diode concurrently with other semiconductor devices on a large scale semiconductor wafer includes utilizing a composite mask to define one or more stable buried zener diodes, one or more additional semiconductor devices, and a number of isolation regions. After applying a screen oxide over selected portions of the semiconductor wafer, subsequent ion implantation steps and additional masking steps concurrently form the stable buried zener diode along with additional and different semiconductor devices utilizing conventional ion implant bi-polar processing techniques.

Abstract: A new diode structure is provided by bonding two semiconductor materials together having a low capacitance, a large contact area and mechanical ruggedness. The cross-sectional area of at least one of the semiconductor materials is reduced in the region of the bond resulting in a structure with either an hourglass or truncated hourglass-like cross-section. A diode PN junction is contained in the neighborhood of the area of reduced cross section. The diode so constructed provides a sufficient spacing between the unbonded semiconductor regions to reduce total packaged diode capacitance without introducing a spacer layer. The diode is processed to limit the area of the PN junction formed therein to the region of the bonding between the semiconductor materials, without limiting the metallized contact area, further controlling the diode capacitance as well as other electrical characteristics.

Abstract: A load current sharing circuit is disclosed that allows multiple independent power modules, either switching or linear, to be connected in a parallel configuration such that each module delivers only its proportionate share of the load current. Each module measures the common output voltage, compares that voltage to an internal reference voltage signal, and generates an error voltage signal to be used as feedback for regulating its output voltage. The internal reference voltage signal is a function of the extent to which the current within each module differs from the current of the module with the highest current. That module functions as the master, and all the other modules act as slaves. Each slave increases its share of the load current so as to asymptotically approach the load current of the master to within a preset offset voltage, while the load current of the master decreases.

Abstract: A high-accuracy MOSFET-switched sampling circuit feeds charge feedthrough error to a load as well as to a dummy load during DC input signal sampling by a switching MOSFET, thereby reducing storage of the charge feedthrough error on the load to the extent that the charge feedthrough error is rather stored on the dummy load. During AC input signal sampling, the high-accuracy MOSFET-switched sampling circuit isolates the AC input signal from the dummy load. Charge feedthrough error produced by an isolating MOSFET that isolates the AC input signal from the dummy load is exactly compensated by a phase-opposed compensating MOSFET positioned in the DC input signal path. The dummy load and the load may be active as well as passive and may be selected to have equal and unequal electrical characteristics.

Abstract: An analog computational circuit, for transforming an input voltage into an output voltage or current variable according to a selected transfer function, including a plurality of current sources having a common input and a common current output. Each of the current sources is energizable in response to an input voltage as it exceeds a selected input voltage threshold associated with each of the current sources. There are means coupled to the current sources for establishing the input voltage threshold associated with each of the current sources. Also included are means coupled to each of the current sources for establishing the selected transfer function of the computational circuit. Each of the current sources is adapted to begin conducting current in response to an input voltage which exceeds its associated input voltage threshold, and to provide an attenuated output current proportional to the input voltage, the proporation established by the selected transfer function.

Abstract: An improved fast track and hold amplifier having a hold capacitor in which in one embodiment a diode switching bridge is connected in a feedback loop of a transimpedance amplifier and in which in another embodiment a feedback resistor is connected in the feedback loop of a transimpedance amplifier is disclosed. The transimpedance amplifier provides a current signal representative of the current necessary to drive the voltage on the hold capacitor to the level of the input analog signal, and current mirrors connected to the hold capacitor respond to the current signal to charge up the hold capacitor to the level of the input signal by supplying a charging current to the hold capacitor that is a multiple of the current necessary. Devices constructed in accordance with the invention exhibit slew rates, droop rates and bandwidths comparable to or better than those of the heretofore known devices but at substantially lower power levels than heretofore possible.

Abstract: A method for processing at least two semiconductor wafers for producing a partially processed semiconductor substrate which can be subsequently further processed utilizing conventional planar semiconductor processing techniques to achieve a complementary semiconductor structure in which a plurality of matched semiconductor elements can be formed. An embedded silicide layer in the bonded semiconductor substrate acts as a conduit for horizontally dispersing dopant during the diffusion process. The dopant subsequently up-diffuses into an adjacent silicon region forming generally uniform and shallow, buried layer regions.

Abstract: A current sensor and limiter provides an output current having a value which is a sum of at least a portion of an input current and a reference current. The current sensor senses an input current which exceeds the reference current, and activates a current shunt which diverts from the input current, an amount of current which is equal to the amount of current by which the input current exceeds the reference current.

Abstract: A power supply reset circuit with a PNP transistor for detecting saturation of an NPN transistor and resetting a fault latch. The PNP and NPN transistors may be separate, discrete components. A preferred embodiment includes a vertical NPN transistor formed in a semiconductor substrate and includes a base, emitter and collector region. The functional, lateral PNP transistor is also fashioned in the semiconductor substrate and has a base region formed by the collector region of the NPN transistor, an emitter region formed by the base region of the NPN transistor, and a distinct, separate collector region disposed in selected proximity to the base and emitter region of the vertical NPN transistor, forming a saturation detector.

Abstract: A process for fabricating a semiconductor device by forming a diffusion region in a first semiconductor wafer and bonding the surface of the first semiconductor wafer having the diffused region to a second semiconductor wafer to form a low resistance buried layer. The process includes further diffusion to provide an external electrical contact with the buried layer. Further enhancements are provided by selectively forming voids and/or selectively applying materials of greater and lesser conductivity on at least one of the semiconductor wafers before bonding, forming complex internal semiconductor structures in the bonded wafer structures.

Abstract: A hermetically sealed, surface mount chip carrier for a semiconductor device is disclosed. The chip carrier is formed of a plurality of layers of conductive material and insulating material. A cavity adapted to receive the semiconductor device is provided within the layers. The device is electrically connected to the conductive layers via electrical conductors bonded to exposed surfaces or shelves on selected ones of the conductive layers. The layers have a continuous periphery to eliminate gaps or vertical discontiniuties in the chip carrier. The conductive and insulating layers have similar coefficients of thermal expansion to provide unitary expansion and contraction of the entire carrier so as to maintain a hermetic seal in the chip carrier when subjected to thermal stresses.

Abstract: A high current gain high-frequency planar process PNP transistor comprising an emitter region and a surrounding annular collector. The surface of the transistor is covered with an insulative oxide layer, with an aperture to the emitter region. An overlaying metal layer is provided which substantially covers the base region between the emitter and collector. Connection to the emitter region is provided with an extension of the metal surface to the aperture. However except for this connection, the surface area above the emitter region is not covered by the metal layer. The resulting transistor provides a high-frequency PNP transistor with significantly enhanced Beta.

Abstract: A current-limiting circuit providing a foldback limiting action which is compensated for the temperature coefficient of the sensing resistor. Temperature compensation and voltage-related signals are combined with a multiplier circuit providing a multiplier output which is compared to the voltage developed across the sense resistor to produce a current control or current limiting indicating signal. One embodiment of the present invention is implemented in a monolithic integrated circuit including an aluminum sense resistor, and the temperature compensation selected to substantially eliminate the effects of the temperature coefficient of the aluminum sense resistor, resulting in a more stable foldback current limiting characteristic over an extended temperature range.

Abstract: A bipolar junction structure comprising a Schottky barrier rectifying contact juxtaposed to a p-n junction having the distribution of p+ diffusions common to a guard ring structure on the Schottky barrier area.

Abstract: A high speed analog amplifier having a differential input and provides a single output signal which corresponds to the absolute value of the input voltage. Furthermore, the amplifier provides a selectable output offset voltage which is proportional to a selected reference voltage. Moreover, the reference voltage alone is sufficient to operate the amplifier, eliminating additional power supply connections.

Abstract: A voltage drop generator having a current source having reduced sensitivity to transistor base-emitter voltage process and temperature induced variations, is used to generate a precise voltage drop across a resistor. Transistor emitter area ratios are selected and an additional resistance is used in conjunction with the selected ratios to reduce the sensitivity (of the output voltage drop) to base-emitter voltages, to provide substantial improvement in process and temperature dependent output variations.

Abstract: A band-gap voltage reference having reduced output voltage noise. The invention embraces several novel concepts, including the optimization of transistor area ratios as used in the band-gap device, the selection of multiple transistors in the Vbe, the section of the current range for the band-gap device, resistive loads to provide minimum load noise and selective signal filtering before the output amplifier. The resulting device according to the present invention exhibits lower output voltage noise than previous band-gap voltage references, without sacrificing other important voltage reference parameters, such as line regulation, load regulation, temperature coefficient, and stability.

Abstract: A low voltage lockout circuit preferably of integrated circuit form to provide a lockout signal when an internally generated reference voltage is insufficient. According to the present invention, a reference voltage is produced by passing a constant current through a reference voltage element, such as a zener diode. Insufficient reference voltage caused by a low power supply input voltage is detected by sensing the saturation of the constant current source. The present invention indicates the precise point of saturation of the constant current source and produces a lockout signal for use by other portions of the integrated circuit, or external devices. The lockout signal also indicates the minimum usable power supply input voltage. The constant current source and the saturation detection element are combined and implemented within a single semiconductor structure.

Abstract: An adjustable threshold window circuit having low-input bias current and constant percentage threshold hysteresis. The window circuit defines an upper reference voltage and a lower reference voltage, both simultaneously adjusted from a common signal wherein the upper threshold voltage increases as the lower voltage threshold decreases to define a voltage window. The threshold voltages are received by a comparator circuit which receives signals to be compared to the upper and lower voltage references, and provides an overvoltage and undervoltage fault indication when the received signals exceed the respective thresholds. Theovervoltage and undervoltage fault signals are received by the window circuit, providing an adjustment of the reference voltages to produce a hysteresis effect.

Abstract: A power driver circuit which provides a low voltage drop thereacross when turned on, without being driven into hard saturation. Hard saturation of the circuit according to the present invention is prevented by additional circuit elements which allow the transistor output circuit to be turned on while diverting excess drive current away from the input transistor. As a result, the driver circuit can provide the low saturation voltage and avoid unnecessary saturation of the output transistor while maintaining high-speed switching operation. The circuit may be implemented by discrete components, by a single integrated circuit or part of a larger integrated circuit.