Patents Assigned to Volterra Semiconductor Corporation
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Patent number: 8680676Abstract: A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.Type: GrantFiled: February 4, 2013Date of Patent: March 25, 2014Assignee: Volterra Semiconductor CorporationInventors: Ilija Jergovic, Efren M. Lacap
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Patent number: 8674802Abstract: A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core including a first and a second end magnetic element and a plurality of connecting magnetic elements disposed between and connecting the first and second end magnetic elements. A respective first and second single turn foil winding is wound at least partially around each connecting magnetic element. Each foil winding has two ends forming respective solder tabs.Type: GrantFiled: October 7, 2011Date of Patent: March 18, 2014Assignee: Volterra Semiconductor CorporationInventor: Alexandr Ikriannikov
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Patent number: 8674798Abstract: An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding fauns a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.Type: GrantFiled: January 6, 2012Date of Patent: March 18, 2014Assignee: Volterra Semiconductor CorporationInventor: Alexandr Ikriannikov
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Patent number: 8664767Abstract: An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion.Type: GrantFiled: April 24, 2012Date of Patent: March 4, 2014Assignee: Volterra Semiconductor CorporationInventors: Ilija Jergovic, Efren M. Lacap
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Patent number: 8664728Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.Type: GrantFiled: January 14, 2009Date of Patent: March 4, 2014Assignee: Volterra Semiconductor CorporationInventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
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Patent number: 8647950Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: GrantFiled: August 10, 2012Date of Patent: February 11, 2014Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8638187Abstract: An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.Type: GrantFiled: November 15, 2011Date of Patent: January 28, 2014Assignee: Volterra Semiconductor CorporationInventor: Alexandr Ikriannikov
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Patent number: 8629669Abstract: The disclosed embodiments of voltage regulators incorporate a current mode control architecture. In one embodiment, a comparator mechanism triggers a transition in a power switch when the error in the regulated output voltage is equal to a proportionally scaled value of current provided at an output filter. The voltage regulator includes a power switch having an input and an output. The power switch is configured to provide a first voltage during a first conduction period and a second voltage during a second conduction period. An output filter is coupled between the power switch output and an output terminal to be coupled to a load. A comparator mechanism has a reference input coupled to a reference voltage, a feedback input coupled to sense a feedback voltage at the output filter, a current sensing input coupled to sense a current sensing voltage corresponding to a current provided to the output filter, and an output in communication with the power switch input.Type: GrantFiled: October 14, 2010Date of Patent: January 14, 2014Assignee: Volterra Semiconductor CorporationInventors: David Christian Gerard Tournatory, Seth Kahn
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Patent number: 8598000Abstract: A method of making a transistor is disclosed. The method starts with applying a first photoresist and performing a first etching of the first side of a gate where the gate includes an oxide layer formed over a substrate and a conductive material formed over the oxide layer. The first etching is followed by implanting an impurity region into the substrate while using the first photoresist and the conductive material as a mask making the implantation of the impurity region self-aligned to the gate. The implantation is followed by applying a second photoresist and performing a second etching of the second side of the gate.Type: GrantFiled: March 30, 2010Date of Patent: December 3, 2013Assignee: Volterra Semiconductor CorporationInventor: Marco A. Zuniga
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Patent number: 8574973Abstract: An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.Type: GrantFiled: March 13, 2013Date of Patent: November 5, 2013Assignee: Volterra Semiconductor CorporationInventors: Budong You, Marco A. Zuniga
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Patent number: 8553438Abstract: A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes one or more slaves, and each slave includes a switching circuit which serves as a power switch for alternately coupling and decoupling the input terminal to an intermediate node. The voltage regulator also includes a filter coupled to the slaves, the filter including one or more inductor banks each of which having a predetermined number of inductors.Type: GrantFiled: August 31, 2011Date of Patent: October 8, 2013Assignee: Volterra Semiconductor CorporationInventor: Aaron M. Schultz
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Patent number: 8547076Abstract: A control system for regulating an output voltage of a DC-DC converter having N phases, where N is an integer greater than one, includes a pulse generator and a frequency divider. The pulse generator generates a stream of fixed on-time pulses, each pulse triggered in response to current through an alternating one of the N phases falling to a threshold value. The frequency divider divides the stream of fixed on-time pulses into N phase signals for controlling the N phases. A method for regulating an output voltage of a DC-DC converter having N phases, includes the following steps: (1) generating a stream of fixed on-time pulses, each pulse triggered in response to current through an alternating one of the N phases falling to a threshold value, and (2) dividing the stream of fixed on-time pulses into N phase signals for controlling the N phases.Type: GrantFiled: March 10, 2011Date of Patent: October 1, 2013Assignee: Volterra Semiconductor CorporationInventor: Alexandr Ikriannikov
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Publication number: 20130234249Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.Type: ApplicationFiled: April 24, 2013Publication date: September 12, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Budong You, Yang Lu
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Publication number: 20130229249Abstract: An M phase coupled inductor includes a magnetic core including a first end magnetic element, a second end magnetic element, and M legs disposed between and connecting the first and second end magnetic elements. M is an integer greater than one. The coupled inductor further includes M windings, where each winding has a substantially rectangular cross section. Each one of the M windings is at least partially wound about a respective leg.Type: ApplicationFiled: March 10, 2013Publication date: September 5, 2013Applicant: VOLTERRA SEMICONDUCTOR CORPORATIONInventors: Jieli Li, Charles R. Sullivan, Angel Gentchev
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Patent number: 8526211Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.Type: GrantFiled: July 30, 2012Date of Patent: September 3, 2013Assignee: Volterra Semiconductor CorporationInventor: Marco A. Zuniga
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Publication number: 20130222099Abstract: An M phase coupled inductor includes a magnetic core including a first end magnetic element, a second end magnetic element, and M legs disposed between and connecting the first and second end magnetic elements. M is an integer greater than one. The coupled inductor further includes M windings, where each winding has a substantially rectangular cross section. Each one of the M windings is at least partially wound about a respective leg.Type: ApplicationFiled: March 10, 2013Publication date: August 29, 2013Applicant: VOLTERRA SEMICONDUCTOR CORPORATIONInventor: VOLTERRA SEMICONDUCTOR CORPORATION
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Publication number: 20130207627Abstract: Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, systems, and methods for virtual output voltage sensing for feed-forward control of a voltage regulator. A buffer has an input coupled to sense a monitored signal indicating a duty cycle of switch circuitry coupled to an output filter of the voltage regulator. The buffer is configured to provide at an output, responsive to the monitored signal, a buffer output signal having a high reference voltage for a high side on time and a low reference voltage for a low side on time of the switch circuitry. A filter is coupled to receive and filter the buffer output signal to provide a feed-forward signal indicating the output voltage of the voltage regulator. Control circuitry is configured to control the switching of the switch circuitry responsive to the feed-forward signal.Type: ApplicationFiled: February 7, 2013Publication date: August 15, 2013Applicant: VOLTERRA SEMICONDUCTOR CORPORATIONInventor: VOLTERRA SEMICONDUCTOR CORPORATION
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Publication number: 20130200452Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.Type: ApplicationFiled: January 14, 2013Publication date: August 8, 2013Applicant: VOLTERRA SEMICONDUCTOR CORPORATIONInventor: Volterra Semiconductor Corporation
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Publication number: 20130187737Abstract: An M phase coupled inductor includes a magnetic core including a first end magnetic element, a second end magnetic element, and M legs disposed between and connecting the first and second end magnetic elements. M is an integer greater than one. The coupled inductor further includes M windings, where each winding has a substantially rectangular cross section. Each one of the M windings is at least partially wound about a respective leg.Type: ApplicationFiled: March 10, 2013Publication date: July 25, 2013Applicant: VOLTERRA SEMICONDUCTOR CORPORATIONInventor: VOLTERRA SEMICONDUCTOR CORPORATION
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Patent number: 8487604Abstract: An asymmetrical coupled inductor includes a first and a second winding and a core. The core is formed of a magnetic material and magnetically couples together the windings. The core is configured such that a leakage inductance value of the first winding is greater than a leakage inductance value of the second winding. The coupled inductor is included, for example, in a multi-phase DC-to-DC converter. A DC-to-DC converter including a symmetrical coupled inductor includes at least one additional inductor electrically coupled in series with one or more of the coupled inductor's windings. A controller for a DC-to-DC converter including a first phase having an effective inductance value greater than an effective inductance value of a second phase is configured to shut down the second phase while the first phase remains operational during a light load operating condition.Type: GrantFiled: December 10, 2012Date of Patent: July 16, 2013Assignee: Volterra Semiconductor CorporationInventors: Alexandr Ikriannikov, Ognjen Djekic