Patents Assigned to Western Digital Corporation
  • Patent number: 6850443
    Abstract: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: February 1, 2005
    Assignees: SanDisk Corporation, Western Digital Corporation
    Inventors: Karl M. J. Lofgren, Robert D. Norman, Gregory B. Thelin, Anil Gupta
  • Patent number: 6771468
    Abstract: A slider utilizes a triple-etch, high pitch-stiffness side rail ABS design. The slider is characterized by a relatively deep shallow recession at its leading edge, which maximizes the cavity area while at the same time increases the pitch angle to achieve DLC pad clearance as required by smooth media ABS designs. The slider ABS has a shallower recession at the trailing edge, which provides low gram-load sensitivity and low flying standard deviation. The slider ABS further presents a decreased sensitivity in response to altitude variations.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: August 3, 2004
    Assignee: Western Digital Corporation
    Inventors: Pablo Gabriel Levi, Manuel Anaya Dufresne, Biao Sun, Forhad Hossain
  • Patent number: 6715044
    Abstract: A memory system includes an array of solidstate memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: March 30, 2004
    Assignees: SanDisk Corporation, Western Digital Corporation
    Inventors: Karl M. J. Lofgren, Jeffrey Donald Stai, Anil Gupta, Robert D. Norman, Sanjay Mehrotra
  • Publication number: 20030227804
    Abstract: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.
    Type: Application
    Filed: May 2, 2003
    Publication date: December 11, 2003
    Applicant: SanDisk Corporation and Western Digital Corporation
    Inventors: Karl M.J. Lofgren, Robert D. Norman, Gregory B. Thelin, Anil Gupta
  • Patent number: 6594183
    Abstract: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: July 15, 2003
    Assignees: SanDisk Corporation, Western Digital Corporation
    Inventors: Karl M. J. Lofgren, Robert D. Norman, Gregory B. Thelin, Anil Gupta
  • Patent number: 6281652
    Abstract: Disclosed is a method in a disk drive that allows the functionality of a single high-resolution DAC to be replicated with a pair of lower-resolution DACs that are operated in a unique manner that provides monotonic behavior and reduces both differential and integral non-linearity. The two lower-resolution DACs take up substantially less space that one higher-resolution DAC when implemented in a semiconductor die. The method combines coarse values from one DAC with fine values from the other DAC to form a combined analog output signal within operational segments that collectively span a range of N-bit demands. The method operates such the operational segments overlap one another by 50 percent, with an endpoint of each operational segment ending near a center of an overlapped operational segment.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: August 28, 2001
    Assignee: Western Digital Corporation
    Inventors: Robert P. Ryan, George S. Bouchaya
  • Patent number: 6271604
    Abstract: The invention is an integrated computer module adapted for removable insertion into a docking bay in a host assembly wherein such module includes an enclosure, a main printed circuit board assembly, a module connector for connection to a host connector, a disk drive, and a locking mechanism for automatically engaging a projecting member in the docking bay to secure the module therein to prevent loss of data due to a surprise removal of the module. The preferred locking mechanism involves a solenoid and a latch plate with a downwardly-opening notch that engages a recess on the projecting member. The preferred locking mechanism is biased closed such that the locking mechanism locks the module in by default and must be energized for removal.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: August 7, 2001
    Assignee: Western Digital Corporation
    Inventors: Charles W. Frank, Jr., Thomas D. Hanan, Wally Szeremeta, Marc B. Goldstone
  • Patent number: 6262857
    Abstract: A disk drive includes a disk having a disk surface, the disk surface having a plurality of tracks arranged in an embedded servo format. The disk surface includes a plurality of radially-extending user-data regions and a plurality of radially-extending servo-data regions. Each user-data region has a plurality of data zones in each of which user data are stored in a plurality of track segments at a data channel frequency particular to that data zone. Each servo-data region has a plurality of servo zones in each of which servo data are stored in a plurality of track segments at a servo channel frequency particular to that servo zone. The servo channel frequency differs from the data channel frequency for at least one track.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: July 17, 2001
    Assignee: Western Digital Corporation
    Inventors: Richard William Hull, Vafa James Rakshani, David Price Turner, Robert Leslie Cloke
  • Patent number: 6263459
    Abstract: A method for reassigning a defective data site on a disk surface of a disk drive during a write operation. When a write error is detected while writing a data block to a user data site, a write error recovery procedure is performed on the user data site. If the write error recovery procedure determines that the user data site contains an unrecoverable error, the data block is written to a spare data site located at a different area of the disk surface, and a cross-reference entry for the reassignment is stored in memory on the disk drive. Upon completion of the write operation, the user data sites encountering write errors are reassigned to the spare data sites. The reassignment operation includes marking all user data sites encountering write errors as defective data sites, adding all user data sites encountering write errors to a list of defective data sites, and writing the reassignment cross reference entries stored in the disk drive memory to the disk surface.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: July 17, 2001
    Assignee: Western Digital Corporation
    Inventor: Mark R. Schibilla
  • Patent number: 6256695
    Abstract: The present invention provides a disk drive system employing a method of analyzing disk drive failure wherein a disk drive target controller is logically connected to an initiator on a SCSI bus. The method includes storing SCSI bus state information upon the receipt of a SCSI bus reset condition. SCSI bus state information is maintained, wherein the SCSI bus state information corresponds to the logical connection between the initiator and the disk drive target controller on the SCSI bus. A SCSI bus reset condition is detected. The maintained SCSI bus state information is stored upon detection of the SCSI bus reset condition. Actions are preformed to reset devices connected to the SCSI bus, including resetting the disk drive target controller. The SCSI bus state information can be subsequently analyzed to aid in determining the cause of the SCSI bus reset condition.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: July 3, 2001
    Assignee: Western Digital Corporation
    Inventor: Jeffrey L. Williams
  • Patent number: 6249393
    Abstract: A disk drive with a write condition detector generates a write condition signal from a reference signal to warn of a high fly write or a low fly write. The reference signal is generated by the disk drive read/write head by reading a reference segment. The write condition detector processes fly-height varying components from the reference signal. The write condition detector generates a write condition signal, responsive to the fly-height varying components and the threshold, that indicates that the writing of data in a user data segment during the write operation is unsafe when the head deviates from its operating flying-height. The threshold is computed using zone coefficients determined during an intelligent burn in of the disk drive, and is based on a nominal fly height. The write condition signal is processed by a microprocessor that instructs a disk controller to deactivate a write gate controlling the write operation.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: June 19, 2001
    Assignee: Western Digital Corporation
    Inventors: Russell A. Billings, Shafa Dahandeh, Mark D. Hagen
  • Patent number: 6246346
    Abstract: A storage system employs a method for encoding a sequence of input data blocks into a sequence of codewords. Each input data block includes a first predetermined number of bits (the data block length). Each codeword includes a second predetermined number of bits (the codeword length). The code rate, i.e., the ratio of the first number to the second number, is greater than ¾. The method is performed in a sampled-data channel in a storage system; and the channel includes a circuit the performance of which is adversely affected by an excessive run length of bits between occurrences of a predetermined influential pattern. Preferably, the influential pattern is a two-bit sequence of adjacent 1's, which favorably influences the performance of a timing recovery circuit. The method includes receiving the sequence of input data blocks and generating the sequence of codewords responsive to the received sequence of input data blocks.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: June 12, 2001
    Assignee: Western Digital Corporation
    Inventors: Robert Leslie Cloke, Patrick James Lee, Steven William McLaughlin
  • Patent number: 6243223
    Abstract: A disk drive has a sampled servo system controller and a disk with a plurality of angularly spaced servo wedges. Each of the servo wedges contains angularly aligned servo burst fields that are radially adjacent to one another and spaced apart by an erase field. In order to eliminate or minimize servo position signal errors caused by a wide-reading transducer head encountering signals from both of a pair of angularly aligned servo burst fields, the servo burst fields are recorded in opposing phase.
    Type: Grant
    Filed: January 15, 1998
    Date of Patent: June 5, 2001
    Assignee: Western Digital Corporation
    Inventors: Timothy J. Elliott, Steven M. Reiser
  • Patent number: 6223303
    Abstract: The present invention provides a method of operating a disk drive having data sites on a disk for recording data thereon. The disk drive is connectable to a host computer and maintains a defect table comprising defective sites reportable to the host computer. The method includes the step of discovering a defective data site on the disk. The defective data site is bounded with a first tier of marginal data sites which are selected based on their proximity to the defective data site. The first tier of marginal data sites is bounded with a second tier of reserved data sites which are selected based on their proximity to the first tier of marginal data sites. The locations of the defective data site, the first tier of marginal data sites and the second tier of reserved data sites are stored in a defect table. The defective data sites and the first tier of marginal data sites are marked as defective sites reportable to the host.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: April 24, 2001
    Assignee: Western Digital Corporation
    Inventors: Russell A. Billings, Kim Edward Russell
  • Patent number: 6215616
    Abstract: A spindle motor for a disk drive includes a shaft, an upper bearing, a lower bearing, a stator, a hub and wire guide body. The upper bearing surrounds the shaft. The lower bearing surrounds the shaft, is spaced-apart from the upper bearing, and includes an inner race. The stator surrounds the shaft between the upper bearing and the lower bearing, and includes a stator wire extending from a stator core. The hub is concentrically positioned about the stator. The wire guide body is secured between the shaft and the lower bearing, and includes a generally cylindrically shaped surface and a channel. The channel is sized to receive the stator wire and is formed adjacent to the cylindrically shaped surface such that the channel opens into at least one of the shaft and the inner race.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: April 10, 2001
    Assignee: Western Digital Corporation
    Inventors: Bang Phan, Joseph H. Sassine
  • Patent number: 6208486
    Abstract: A disk drive includes a disk drive base, a spindle motor, a first disk and a disk clamp. The rotary hub of the spindle motor includes a generally cylindrically-shaped hub wall and a hub flange including an inner annular surface adjacent to the hub wall, an outer annular surface and a flange land portion integrally formed with the hub flange. The land portion is positioned between the annular surfaces and defines a disk contact surface projecting above the annular surfaces, the disk contact surface being substantially centered on the hub flange. The first disk is supported by the disk contact surface to form a clearance between the annular surfaces and the first disk. A second disk may be coupled to the spindle motor and an annular disk spacer may be positioned between the disks. The annular disk spacer includes a first spacer surface facing the first disk and a second spacer surface facing the second disk.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: March 27, 2001
    Assignee: Western Digital Corporation
    Inventors: John R. Gustafson, Payman Hassibi, Kamran Oveyssi
  • Patent number: 6208477
    Abstract: In a hard disk drive, a semiconductor chip includes a circuit used in a built-in self test (“BIST”) to determine an amplitude of a dibit echo for characterizing nonlinear distortion of a readback signal. Preferably, write precompensation is performed based on results of the BIST to minimize distortion attributable to intersymbol interference. A generator is used to generate a maximal length pseudo-random sequence. This maximal length pseudo-random sequence is input to a correlator which performs a correlation between the maximal length pseudo-random bit sequence and a readback signal responsive to the pseudo-random sequence that was stored onto a disk of the hard disk drive. In one embodiment, a seed value stored in memory is loaded into the generator upon detection of a synchronization signal read from the disk. With the appropriate seed value loaded into the generator, a specific pseudo-random bit sequence corresponding to a sample point of interest is then generated.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: March 27, 2001
    Assignee: Western Digital Corporation
    Inventors: Robert Leslie Cloke, Patrick James Lee
  • Patent number: 6204988
    Abstract: The invention is a method of characterizing the frequency response of the servo control system in a disk drive having a sampled servo system having a sampling rate and a nominal bandwidth, wherein the sampled servo system comprises a plant and a servo controller that controls the plant using a compensator and a gain element with a nominal open loop gain. The invention is, in more detail, a method for adaptively modifying the servo controller to compensate for plant variations which are incompatible with the nominal gain and bandwidth, including the steps of implementing a self-generated bode plot to determine a gain margin and a phase margin, and if the gain margin is not greater than a predetermined minimum, adjusting the open loop gain of the servo controller to provide a gain margin which is greater than the predetermined minimum at a bandwidth which is different than the nominal bandwidth; and adjusting the compensator to provide a phase margin which is greater than a predetermined minimum.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: March 20, 2001
    Assignee: Western Digital Corporation
    Inventors: Raffi Codilian, Edgar De-Jia Sheh, Jie Yu
  • Patent number: 6205494
    Abstract: A command queuing engine in a target controller ASIC automatically detects sequential commands received from an initiator and generates a linked list of data transfer descriptors for the sequential commands. The data transfer descriptors are automatically processed by the command queuing engine to reduce command overhead from interrupt processing by a microprocessor in the target controller, thereby improving the performance of the target controller.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: March 20, 2001
    Assignee: Western Digital Corporation
    Inventor: Jeffrey L. Williams
  • Patent number: 6200441
    Abstract: A stationary vacuum deposition machine for use in a method for processing substrates to make magnetic hard disks includes a series of stations and a transport. The series of stations includes an entrance station for receiving substrates into the machine and a predetermined station. The transport operates in a cycle with each cycle including a transport phase and a stationary phase. The transport causes all the substrates that are in the machine to be moved during the transport phase, and be temporarily held stationary during the stationary phase, such that during each stationary phase a predetermined one of the stations is occupied by one of the substrates while each of a plurality of others of the stations is occupied by a respective one of a plurality of others of the substrates. The machine further includes a plurality of vacuum deposition stations and a scanning beam generator.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: March 13, 2001
    Assignee: Western Digital Corporation
    Inventors: Stella Zofia Gornicki, Douglas J. Krajnovich