Abstract: A method for yield correlation for semiconductor chips, in accordance with the present invention, includes providing test data for a plurality of tests on each of a plurality of semiconductor chips. A global parameter is assigned to each chip as a quality measure based on the test data for that chip. Values for a plurality of parameter classes are determined, and each parameter class represents a parameter measured for each chip tested. A correlation between the values of the parameter classes and the global parameter values for the plurality of chips is then determined. The correlation for each of the parameter classes is compared to identify at least one parameter class, which detracts from chip yield.

Abstract: A method of increasing the channel length for small semiconductor devices having decreased gate dimensions, thus reducing or eliminating short channel effects for corner devices. The method generally includes forming a gate electrode and defining first and second active areas both adjacent to the gate electrode, which in turn creates a first corner and a second corner. The geometrical shape and position of the first and second active areas with respect to the gate electrode increase the channel length to be longer the gate electrode length. For example, the first corner is positioned offset with respect to the second corner relative to the gate electrode and the carrier channel is a linear segment connecting the first corner to the second corner. In another embodiment, the carrier channel includes multiple segments. The increased channel length reduces or eliminates short channeling effects without affecting the threshold voltage.

Abstract: A manufacturing process for producing dynamic random access memories (DRAMs) having redundant components includes steps for concurrently forming normal (i.e. non-fused) contacts to components of the DRAMs and anti-fused contacts to the redundant components. The process by which the normal and anti-fused contacts are made is readily implemented using standard integrated circuit processing techniques. An anti-fuse contact (20) and a normal (i.e. non-fused) contact (10) are formed by opening respective contact areas in a dielectric (110), selectively forming an insulating layer (210) over the anti-fuse contact, applying polysilicon (212, 410) to cover the insulating layer of the anti-fuse contact and to fill the opening over the normal contact. In one embodiment of the invention, the circuit region served by the anti-fuse contact is subject to ion implantation (810) to improve its conductivity before the anti-fuse contact is formed.

Abstract: An apparatus and method of tungsten via fill using a low pressure, 2-step nucleation tungsten deposition process. The tungsten via fill includes a silane soak, a nucleation film growth, and a bulk tungsten film deposition. The nucleation film growth is a low pressure, 2-step process including a controlled first nucleation film growth and a second nucleation film growth. A wafer fabricating system that includes a film depositing system and a control system is used. The film depositing system includes a reaction chamber with at least one silane-containing gas source, a tungsten-containing gas source, and a substrate heating source. The control system instructs the silane-containing gas source and the tungsten-containing gas source to flow with a significantly higher ratio of silane-containing gas (SiH4) to form a first silane-rich nucleation layer. The control system then instructs the gas sources to flow with a higher ratio of tungsten-containing gas, such as WF6, to form a second tungsten nucleation layer.

Abstract: A method for probing a semiconductor component for an active single device test, in accordance with the present invention, includes providing a semiconductor device to be tested and accessing at least one component of the semiconductor device by simultaneously milling a hole and depositing a plug in the hole to connect to the at least one component. A circuit is provided through the plug to make electrical measurements of the semiconductor device.

Abstract: A method for rounding corners of a silicon substrate, in accordance with the present invention, includes forming a plateau on a silicon substrate having corners at edges of the plateau. A mask is formed on a top surface of the plateau, which is recessed back from vertical edges of the plateau to provide exposed horizontal portions. Fluorine or Argon dopants are implanted at the corners and on the exposed portions, and the substrate is oxidized such that the corners become rounded providing a gradual transition at the edges of the plateau.