Patents Assigned to Xicor, Inc.
  • Patent number: 5434396
    Abstract: A wireless communication system for communicating between a host system and a stand-alone device through an electromagnetic coupling medium is disclosed. The communication system has the capabilities of bi-directional data communications between the host and the stand-alone device and of powering the stand-alone device with energy pulses coupled through the electromagnetic coupling medium from the host. The electromagnetic medium is capable of supporting the bi-directional flow of energy pulses and energy transitions thereof between the host and stand-alone device. In one embodiment, bi-directional communication is provided by transmitting and detecting predetermined numbers of consecutive energy transitions coupled through the medium. Resting durations immediately precede and follow each predetermined number of consecutive energy transitions.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: July 18, 1995
    Assignee: Xicor Inc.
    Inventors: William H. Owen, James M. Jaffe
  • Patent number: 5324676
    Abstract: A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: June 28, 1994
    Assignee: Xicor, Inc.
    Inventor: Daniel C. Guterman
  • Patent number: 5270972
    Abstract: A three-terminal serial-communication peripheral device for low-cost applications is described. The peripheral device comprises a first terminal for receiving a modulated power signal including a source of power and a clocking signal, a second terminal for receiving a reference potential such as a ground reference, and a third terminal for communicating data to and from the peripheral device. The peripheral device further comprises a digital subsystem which exchanges data with an application system. The exchanged data may be stored and retrieved by the digital subsystem, as when the subsystem is a memory unit, or the data may be in the form of measurement data which the peripheral device is supplying to the application system, the measured data being supplied by a sensor of the subsystem. With its three terminals, the peripheral device can communicate data to and from the application system.
    Type: Grant
    Filed: April 14, 1992
    Date of Patent: December 14, 1993
    Assignee: Xicor, Inc.
    Inventors: Gary M. Craig, Clifford A. Zitlaw
  • Patent number: 5219774
    Abstract: An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor deposition (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the apparatus is constructed by forming a first layer of polysilicon, patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness. If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: June 15, 1993
    Assignee: Xicor, Inc.
    Inventor: Gregory S. Vasche
  • Patent number: 5161157
    Abstract: A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: November 3, 1992
    Assignee: Xicor, Inc.
    Inventors: William H. Owen, John Caywood, Joseph Drori, James Jaffe, Isao Nojima, Jeffrey Sung, Ping Wang
  • Patent number: 5153691
    Abstract: A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer.
    Type: Grant
    Filed: August 14, 1991
    Date of Patent: October 6, 1992
    Assignee: Xicor, Inc.
    Inventor: Daniel C. Guterman
  • Patent number: 5153880
    Abstract: A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over the standard signal paths with standard voltage levels of the integrated circuit semiconductor memory array. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell.
    Type: Grant
    Filed: March 12, 1990
    Date of Patent: October 6, 1992
    Assignee: Xicor, Inc.
    Inventors: William H. Owen, John Caywood, Joseph Drori, James Jaffe, Isao Nojima, Jeffrey Sung, Ping Wang
  • Patent number: 5084667
    Abstract: A variable impedance circuit for use in an external circuit is disclosed. The impedance value is selected by an external circuit. The variable impedance is generated between two terminals which are accessible for connection to external circuitry. The impedance provided between these terminals is determined by a control circuit responsive to electrical signals coupled to the control circuit. An internal register in the control circuit stores a value which specifies the impedance between the two terminals. The stored value is copied into a programmable nonvolatile read-only memory in response to a first predetermined electrical signal. Similarly, the value stored in the read-only memory is selectively copied into the internal control circuit register in response to a second predetermined electrical signal.
    Type: Grant
    Filed: December 22, 1989
    Date of Patent: January 28, 1992
    Assignee: Xicor, Inc.
    Inventors: Joseph Drori, William S. Jennings Check, William H. Owen, III
  • Patent number: 5023694
    Abstract: A nonvolatile integrated circuit memory cell (10) is provided which is smaller in size than conventional memory cells and uses only two layers of polysilicon with floating gate portion (50) of the memory cell formed partly from a first polysilicon layer (20) and partly from second polysilicon layer (26), contact between the two portions being made using residual polysilicon bridge or overlapping portion (34) between the two layers. The invention enables programming and erase tunneling oxides to be formed in a single step while maximizing the capacitive coupling between the floating gate (50) and the substrate (12) by forming a silicon dioxide layer (102) between the floating gate and substrate separately from formation of the programming (30) and erase (28) tunneling elements.
    Type: Grant
    Filed: August 3, 1988
    Date of Patent: June 11, 1991
    Assignee: Xicor, Inc.
    Inventor: Bing Yeh
  • Patent number: 5012132
    Abstract: A dual mode high voltage coupler is described for enabling a low current capacity high voltage generator to supply high voltage to an output load, such as a row or word line in an EEPROM memory device during a nonvolatile write or erase operation. The coupler limits the amount of current to defective cells or rows in the memory without limiting current to the cells and rows that are operating normally. In a first mode, a single stage charge pump, including a storage capacitor driven by a periodic voltage signal, develops a metered current through a diode to the output load whose amplitude is equal to the product of the capacitance of the storage capacitor, the change in voltage across the capacitor in each cycle of said periodic signal and the frequency of said signal. In a second mode, said high voltage is coupled directly to said output load without limiting the current whenever the voltage across said load exceeds a predetermined value.
    Type: Grant
    Filed: October 5, 1989
    Date of Patent: April 30, 1991
    Assignee: Xicor, Inc.
    Inventor: Ping Wang
  • Patent number: 5003197
    Abstract: An apparatus for generating and regulating a substrate bias voltage for use in semiconductor devices. The invention comprises a sensor which is responsive to the substrate bias voltage, and generates a continuously variable regulating voltage and a continuously variable oscillator bias voltage. A variable impedance device whose resistance is adjustable over a range of values as a function of said regulating voltage is coupled to a charge pump to control the amount of charge pumped by said charge pump per unit time from the substrate of the semiconductor device. An oscillator whose frequency is continuously controlled by the oscillator bias voltage from the sensor is coupled to said charge pump so as to further control the amount of charge pumped by said charge pump per unit time.
    Type: Grant
    Filed: January 19, 1989
    Date of Patent: March 26, 1991
    Assignee: Xicor, Inc.
    Inventors: Isao Nojima, Ping Wang, Hung Q. Nguyen
  • Patent number: 4980859
    Abstract: A nonvolatile, semiconductor randon access memory cell comprising a static RAM element and a nonvolatile memory element having differential charge storage capabilities is presented. The static RAM and nonvolatile memory elements are interconnected to allow information to be exchanged between two elements, thus allowing the faster static RAM element to serve as the primary memory to the system and allowing the nonvolatile memory element to serve as permanent storage during power-down conditions. In one embodiment, the nonvolatile memory element comprises two electrically erasable PROM devices (EEPROMs). The two EEPROM devices store differential charges corresponding to the complementary outputs of the static RAM element. The nature of the differential charge storage allows lower programming voltages to be used on the EEPROM devices, resulting in increased storage intergrity and increased endurance of the EEPROM devices.
    Type: Grant
    Filed: April 7, 1989
    Date of Patent: December 25, 1990
    Assignee: XICOR, Inc.
    Inventors: Daniel C. Guterman, Isao Nojima, Ping Wang
  • Patent number: 4883976
    Abstract: A substrate voltage bias generator is disclosed including a charge pump whose output is clamped during charge pump capacitor charging cycles to zero volts thereby eliminating a voltage drop associated with prior art clamping diodes. The charge pump further includes a stand-by and booted mode, the stand-by mode providing a first level of output current at a specified generated substrate bias voltage and in the booted mode generating increased output current and voltage. The increased voltage is generated across the charge pump capacitor by a second capacitor that is only operative in the booted mode and whose charge is shared with the charge pump capacitor thereby developing a higher voltage across the charge pump capacitor. The output voltage generated by the substrate bias generator is detected and if it is too low a voltage, the booted mode is turned off. An external signal determines whether the stand-by mode or booted mode are selected.
    Type: Grant
    Filed: December 2, 1987
    Date of Patent: November 28, 1989
    Assignee: Xicor, Inc.
    Inventor: Peter Deane
  • Patent number: 4874967
    Abstract: The voltage clamp circuit can clamp positive and/or negative voltages. The voltage clamp circuit includes voltage sensing and clamping circuit consisting of a chain of series connected diodes connected between an output and a reference terminal of the voltage clamp circuit. A current mirror circuit is connected to the chain of series connected diodes. A current generating circuit is connected to the current mirror circuit and sensing and clamping circuit. The voltage clamp circuit consumes only enough current to develop a threshold voltage across each of the chain of series connected diodes.
    Type: Grant
    Filed: December 15, 1987
    Date of Patent: October 17, 1989
    Assignee: Xicor, Inc.
    Inventor: Peter Deane
  • Patent number: 4829482
    Abstract: A current metering circuit is configured as a single stage charge pump for limiting the current level applied to the tunneling regions of an integrated circuit, nonvolatile, floating gate memory cell. The current metering circuit includes a storage capacitor which has one plate pumped by a periodic signal. The other plate of the capacitor is charged from a voltage that is boot-strapped from the voltage that presently exists across the active tunneling region. More particularly, a high voltage is applied to the drain of a transistor whose gate is connected to the tunneling region. The source of this transistor is coupled to a plate of the storage capacitor. This source develops a voltage equal to the present voltage across the load less the turnon threshold of the transistor. When the periodic signal goes low, the storage capacitor is charged from the voltage appearing at the source of this transistor.
    Type: Grant
    Filed: October 18, 1985
    Date of Patent: May 9, 1989
    Assignee: Xicor, Inc.
    Inventor: William H. Owen
  • Patent number: 4752912
    Abstract: A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described as including four electrode layers, one of which being formed as a substrate coupling electrode. The cell is also described as being relatively process intolerant. The first electrode layer above the substrate is used to mask the diffusion or implantation of the substrate coupling electrode and other regions in the substrate to form self-aligned active devices.
    Type: Grant
    Filed: July 22, 1985
    Date of Patent: June 21, 1988
    Assignee: Xicor, Inc.
    Inventor: Daniel C. Guterman
  • Patent number: 4668932
    Abstract: A variable impedance circuit for use in an external circuit. The impedance value may be altered by an external circuit. The invention consists of a plurality of two terminal impedance elements connected in series. A node is provided between each pair of impedance elements in the series chain. At least one of the first element and last elements in the series chain are connected to terminals which are accessible for connection to the external circuit. Each of the nodes may be connected to a terminal which is also accessible for connection to the external circuit. An electrically reprogrammable read-only memory stores the identity of the node connected such that the identity of this node is retained when power is removed from the invention. When power is returned to the invention, the node which was previously connected to the terminal is automatically reconnected.
    Type: Grant
    Filed: July 26, 1985
    Date of Patent: May 26, 1987
    Assignee: Xicor, Inc.
    Inventors: Joseph Drori, William S. J. Check
  • Patent number: 4617652
    Abstract: Low power consumption methods and apparatus for distributing and controlling on-chip generated high voltage, for programming nonvolatile memory arrays and the like.
    Type: Grant
    Filed: June 6, 1983
    Date of Patent: October 14, 1986
    Assignee: Xicor, Inc.
    Inventor: Richard T. Simko
  • Patent number: 4599706
    Abstract: A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described in a first embodiment as including four electrode layers, one of which being formed as a substrate coupling electrode. A second embodiment includes a three electrode layer device wherein the need for the substrate coupling electrode is eliminated.
    Type: Grant
    Filed: May 14, 1985
    Date of Patent: July 8, 1986
    Assignee: Xicor, Inc.
    Inventor: Daniel C. Guterman
  • Patent number: 4533846
    Abstract: Integrated high voltage clamping methods and devices which provide a controllable "soft" clamping action. The systems are particularly useful for "on-chip" EEPROM high voltage power supplies.
    Type: Grant
    Filed: May 27, 1982
    Date of Patent: August 6, 1985
    Assignee: Xicor, Inc.
    Inventor: Richard T. Simko