Patents Assigned to Zaidan Hojin Handotai Kenkyu Shinkokai
  • Publication number: 20070160093
    Abstract: An electromagnetic wave generator encompasses a first pump beam emitter (2) configured to emit a first pump beam (hv1) having a wavelength larger than one micrometer; a second pump beam emitter (25) configured to emit a wavelength-tunable second pump beam (hv2) having a wavelength larger than one micrometer, the wavelength of which is different from the wavelength of the first pump beam (hv1); a nonlinear optical crystal (19) configured to generate an electromagnetic wave (hv3) of a difference frequency between the first pump beam (hv1) and second pump beam (hv2); and an optical system (M1, M2, 18) configured to irradiate the first pump beam (hv1) and second pump beam (hv2) to the nonlinear optical crystal (19), by adjusting an external intersection angle between the first pump beam (hv1) and second pump beam (hv2) within 0.5° at the difference frequency of 1 THz.
    Type: Application
    Filed: October 29, 2004
    Publication date: July 12, 2007
    Applicant: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Ken Suto, Tetsuo Sasaki, Tadao Tanabe, Tomoyuki Kimura
  • Publication number: 20060113298
    Abstract: An electromagnetic wave irradiation tool encompasses a narrow tube (endoscope probe) (7) defined by an outside diameter of 0.1 mm-20 mm, having an electromagnetic wave irradiation terminal (3) configured to irradiate an electromagnetic wave (2) having a frequency equal to a characteristic frequency of a microorganism (11) at the top of the narrow tube (7) and an electromagnetic wave generation unit (3) configured to generate the electromagnetic wave (2) and to supply the electromagnetic wave (2) to the electromagnetic wave irradiation terminal (3). The electromagnetic wave irradiation tool drives the microorganism (11) into a resonant vibration state selectively so that the microorganism (11) can be destroyed, without giving damages to biological body (1) for medically treating the disease induced by the microorganism (11).
    Type: Application
    Filed: November 27, 2003
    Publication date: June 1, 2006
    Applicant: ZAIDAN HOJIN HANDOTAI KENKYU SHINKOKAI
    Inventor: Jun-ichi Nishizawa
  • Publication number: 20060054940
    Abstract: The ultra high-speed vertical short channel insulated-gate static induction transistor with uniform operating characteristic which has the drain layer 3 consisting of an epitaxial single crystal layer on the main surface 2 of substrate 1, the channel layer 4 with thickness 1000 ? or less on the drain layer, the source layer 5 consisting of an epitaxial single crystal layer on the channel layer 4, and the insulated-gates 6 and 7 on the sidewalls of the drain, the channel, and the source layers. Since the thickness of 1000 ? or less is accurately controlled using the molecular layer epitaxial method and the channel layer 4 is grown up, the X-ray photolithography is not needed. Since the gate oxide film is formed by low temperature CVD using active oxygen, impurity re-distribution does not occur.
    Type: Application
    Filed: September 9, 2005
    Publication date: March 16, 2006
    Applicants: Incorporated Administrative Agency, Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Toru Kurabayashi, Toru Oizumi, Kyouzou Kanamoto, Jun-ichi Nishizawa
  • Patent number: 6977406
    Abstract: The ultra high-speed vertical short channel insulated-gate static induction transistor with uniform operating characteristic which has the drain layer 3 consisting of an epitaxial single crystal layer on the main surface 2 of substrate 1, the channel layer 4 with thickness 1000 ? or less on the drain layer, the source layer 5 consisting of an epitaxial single crystal layer on the channel layer 4, and the insulated-gates 6 and 7 on the sidewalls of the drain, the channel, and the source layers. Since the thickness of 1000 ? or less is accurately controlled using the molecular layer epitaxial method and the channel layer 4 is grown up, the X-ray photolithography is not needed. Since the gate oxide film is formed by low temperature CVD using active oxygen, impurity re-distribution does not occur.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: December 20, 2005
    Assignees: National Institute of Information and Communications Technology, Incorporated Administrative Agency, Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Toru Kurabayashi, Toru Oizumi, Kyouzou Kanamoto, Jun-ichi Nishizawa
  • Patent number: 5883406
    Abstract: A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in the current path to accomplish storing. Since the bulk mobility of a semiconductor is far larger than the surface mobility, the transit time of the carriers is much improved. Furthermore, since each structure of the memory cells is formed perpendicular to the semiconductor surface, the surface occupation area per memory cell is reduced. Thus, a high-speed and high-density semiconductor memory device is provided.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: March 16, 1999
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 5808328
    Abstract: A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in the current path to accomplish storing. Since the bulk mobility of a semiconductor is far larger than the surface mobility, the transit time of the carriers is much improved. Furthermore, since each structure of the memory cells is formed perpendicular to the semiconductor surface, the surface occupation area per memory cell is reduced. Thus, a high-speed and high-density semiconductor memory device is provided.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 15, 1998
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 5663582
    Abstract: A recess-gate type static induction transistor having a high breakdown voltage is provided, which includes an n-type channel region provided over an n.sup.+ -type drain region, p.sup.+ -type elongated gate regions provided in grooves of the channel region, n.sup.+ -type elongated regions formed on the channel region so as to be arranged in parallel with the gate regions, each of which is disposed between the gate regions, and a p.sup.+ -type guard ring region provided in the channel region and arranged to surround the gate regions. The elongated gate regions are coupled to the guard ring region at both edges. In addition, the outer-most elongated gate regions are coupled to the guard ring region along the longitudinal direction, respectively, thereby increasing the breakdown voltage of the device.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: September 2, 1997
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Junichi Nishizawa, Kaoru Motoya, Akira Ito
  • Patent number: 5485017
    Abstract: A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus.
    Type: Grant
    Filed: May 11, 1994
    Date of Patent: January 16, 1996
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 5426314
    Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: June 20, 1995
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Sohbe Suzuki
  • Patent number: 5384476
    Abstract: A semiconductor device having a source region, a drain region and a channel region which are formed in a surface portion of a semiconductor substrate, and a gate formed with a material having a relatively high built-in voltage relative to the source region. This semiconductor device may further include, in the semiconductor substrate to extend along the channel region, a highly-doped region having a conductivity type opposite to that of the source region. This highly-closed region may have an impurity concentration gradient which is greater toward its portion facing the abovesaid surface of the substrate. These arrangements serve to prevent extinction of memory due to current leakage during absence of bias voltage which otherwise would develop in semiconductor devices having short-channel and thin gate oxide layer, and due to irradiation of alpha-particle onto the device.
    Type: Grant
    Filed: June 9, 1987
    Date of Patent: January 24, 1995
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 5373808
    Abstract: An apparatus and a method are presented for preparing a single crystal ingot of a compound semiconductor material which contains a high vapor pressure component. The apparatus includes: a furnace housing 78 housing a cylindrical hermetic vessel 20 having a ceiling plate section 22A and a bottom plate section 42. External heaters 36, 38 and 40 surrounding the hermetic vessel 20, and a vapor pressure control section which communicates hermetically with the vessel 20.
    Type: Grant
    Filed: May 19, 1993
    Date of Patent: December 20, 1994
    Assignees: Mitsubishi Materials Corporation, Research Development Corporation of Japan, Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Koichi Sassa, Takashi Atami, Keiji Shirata
  • Patent number: 5323029
    Abstract: A static induction device (SI device) at least shares a structure in which an SI thyristor, an IGT and a capacitor are merged onto the single monolithic chip. The SI thyristor has a cathode, an anode and a gate regions, and a channel. The IGT has a well on a surface of the channel, a source and drain regions within the well, a gate insulating film on the well, and a gate electrode on the gate insulating film. The capacitor comprises the gate region of the SI thyristor, the gate insulating film on the gate region, and the gate electrode. The cathode and the drain region are connected to each other through a high-conductive electrode.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: June 21, 1994
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 5323028
    Abstract: In a MOS controlled power device, or MOS composite a static induction thyristor, an static induction thyristor (SI thyristor) unit, a MOS transistor connected in cascode relation to the SI thyristor unit and a voltage regulation element are merged onto the single monolithic chip. The SI thyristor unit has a cathode region of first conductivity type having high impurity concentration, an anode and a gate regions of second conductivity type having high impurity concentration, and a channel region of first conductivity type having low impurity concentration. The MOS transistor has a drain region which is the same region as the cathode region, a well or a base of second conductivity type formed adjacent to the channel region of the SI thyristor unit, and a source region of first conductivity type having high impurity concentration. The source region is formed within the well or above the base.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: June 21, 1994
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Sohbe Suzuki
  • Patent number: 5296403
    Abstract: A semiconductor device comprises a vertical MIS-SIT which has a smaller source-to-drain distance for operation at ultra-high speed. The semiconductor device has a substrate crystal for epitaxial growth thereon, least two semiconductor regions of different conductivity types deposited by way of epitaxial growth on the substrate crystal according to either metal organic chemical vapor deposition (MO-CVD) or molecular layer epitaxy (MLE), thereby providing a source-drain structure, a gate side formed by etching the semiconductor regions of the source-drain structure, the gate side comprising either a (111)A face or a (111)B face, and a semiconductor region deposited as a gate by way of epitaxial growth on the gate side according to either MO-CVD or MLE.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: March 22, 1994
    Assignees: Research Development Corp. of Japan, Jun-ichi Nishizawa, Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Toru Kurabayashi
  • Patent number: 5240685
    Abstract: In an apparatus for growing a GaAs single crystal from its melt, As vapor which is controlled appropriately of its pressure is applied from an As chamber to the surface of the GaAs melt in a vessel throughout the growing process through an As passage communicating between the melt vessel and the As chamber, while establishing a gentle temperature gradient in the passage leading from the GaAs melt vessel to the As chamber. Whereby, a GaAs single crystal having a large diameter and a good crystal perfection with minimized deviation from stoichiometry and minimized lattice dislocation can be obtained.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: August 31, 1993
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 5227647
    Abstract: A semiconductor thyristor of the Static Induction type having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary driving gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control. In operation, the driving and non-driving gates coact so that the non-driving gates, having an induced potential lower than the potential applied to the driving gates, absorb charge carriers injected in the channel during thyristor operation.
    Type: Grant
    Filed: January 11, 1991
    Date of Patent: July 13, 1993
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 5175598
    Abstract: A semiconductor thyristor of the Static Induction type having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary driving gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control. In operation, the driving and non-driving gates coact so that the non-driving gates, having an induced potential lower than the potential applied to the driving gates, absorb charge carriers injected in the channel during thyristor operation.
    Type: Grant
    Filed: January 11, 1991
    Date of Patent: December 29, 1992
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 5065206
    Abstract: A semiconductor device comprises a semiconductive substrate of a low impurity concentration, a channel area of a low impurity concentration formed on the substrate, a source area formed on the channel area and having a high impurity concentration of a conductive type opposite to that of the substrate, a drain area formed on the channel area and having a high impurity concentration of a conductive type opposite to that of the substrate, and an accumulating gate area formed on the channel area and having a conductive type same as that of the substrate. The source area and drain area are arranged in a predetermined direction along the substrate. The accumulating gate area comprises a first part sandwiched between the source area and the drain area and extended in a direction crossing the predetermined direction and second and third parts connected with the first part and approximately extended in the predetermined direction.
    Type: Grant
    Filed: January 25, 1989
    Date of Patent: November 12, 1991
    Assignees: Nikon Corporation, Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-Ichi Nishizawa, Takashige Tamamushi, Hideo Maeda
  • Patent number: 5038188
    Abstract: An insulated-gate type transistor having a semiconductor body of a low impurity concentration, a heavily-doped source region of a conductivity type opposite to that of the semiconductor body for supplying charge carriers, a heavily-doped region for receiving the carriers supplied form the source region, both of which regions may be provided separately in a main surface of the body, a channel region located between the source and drain regions for the travel of these carriers, an insulated-gate structure inputted with a gate voltage for controlling the travel of those carriers, a semiconductor region formed in the neighborhood of the source region within the body and having a portion located below the source region and another portion extending beyond therefrom toward the drain region and serving to define the channel region and to increase the ratio of the amount of carriers reaching the drain region to the total amount of the carriers supplied from the source region.
    Type: Grant
    Filed: March 12, 1990
    Date of Patent: August 6, 1991
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 5019876
    Abstract: A high sensitivity semiconductor photo-electric converter is provided by electrically isolating the gate region of a static induction transistor which exhibits non-saturating current versus voltage characteristic. Optically ionized minority carriers are stored in the gate region to control the potential thereof. A semiconductor gate region provided with a insulated gate is very effective to enhance the dynamic range of the converter. Non-saturating characteristic enables enlargement of the output current simply by increasing the drain voltage. A high-speed and high sensitivity image pick-up device can be materialized by integrating a multiplicity of the static induction type photo-electric converter elements. A switching transistor may be merged in the gate region of each photo-electric converter element to enhance the operation speed of the image pick-up device.
    Type: Grant
    Filed: April 4, 1989
    Date of Patent: May 28, 1991
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa