Patents Assigned to Zarlink Semiconductor Inc.
  • Patent number: 7315546
    Abstract: Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: January 1, 2008
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Willem L. Repko, Robertus L. Van Der Valk, Petrus W. Simons, Craig Barrack
  • Publication number: 20070262822
    Abstract: A digitally controlled oscillator (DCO) generating an output clock includes a jitter shaping module for shifting low frequency digital jitter on the output clock into higher frequency jitter.
    Type: Application
    Filed: April 25, 2007
    Publication date: November 15, 2007
    Applicant: ZARLINK SEMICONDUCTOR INC.
    Inventors: Krste Mitric, Slobodan Milijevic
  • Publication number: 20070262819
    Abstract: An automatic gain control unit controls the gain applied to an input signal produced by a microphone subject to ambient noise. The automatic gain control circuit continually monitors the signal level of said input signal. A first gain control circuit decreases the gain applied to the input signal in increments of a first size when the input signal exceeds a first predetermined level. A second gain control circuit increases the gain applied to said input signal in increments of a smaller size when the input signal falls below a second predetermined level and in response to the presence of a speech present signal. The second predetermined level is less than said first predetermined level. In one embodiment, the first gain control circuit controls the analog gain of a codec and the second gain control circuit controls the digital gain of the codec.
    Type: Application
    Filed: April 26, 2007
    Publication date: November 15, 2007
    Applicant: ZARLINK SEMICONDUCTOR INC.
    Inventors: Gary Qu Jin, Yonghong Huang
  • Patent number: 7295559
    Abstract: A method for recovering a service clock through a packet network for the provision of isochronous services uses a two-layer arrangement wherein stable oscillators are provided at the transmitting and receiving nodes. ACR is used to tune the local oscillators over a long period of time. SRTS is used to transfer the service clock except the timestamp information is based on the local oscillators at the transmitting and receiving nodes instead of the common network clock.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: November 13, 2007
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Gord Reesor
  • Publication number: 20070255560
    Abstract: A method of reducing noise in a speech signal involves converting the speech signal to the frequency domain using a fast fourier transform (FFT), creating a subset of selected spectral subbands, determining the appropriate gain for each subband, and interpolating the gains to match the number of FFT points. The converted speech signal is then filtered using the interpolated gains as filter coefficients, and an inverse FFT performed on the processed signal to recover the time domain output signal.
    Type: Application
    Filed: April 25, 2007
    Publication date: November 1, 2007
    Applicant: ZARLINK SEMICONDUCTOR INC.
    Inventor: Kamran Rahbar
  • Patent number: 7280654
    Abstract: An affine projection or like algorithm is used to process a non-stationary signal. The affine projection algorithm creates an inverse matrix and includes a factor ? to avoid numerical instability in the inverse matrix. The factor ? is adaptively adjusted according to the characteristics of the signal.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: October 9, 2007
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Gary Q. Jin
  • Patent number: 7242740
    Abstract: A digital phase locked loop (DPLL) for providing clock synchronization in backplane bus systems has a loop filter with selectable high and low bandwidth modes. The DPLL is thus capable of respectively attenuating or tracking jitter from an input reference clock.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: July 10, 2007
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Menno Tjeerd Spijker, Krste Mitric
  • Patent number: 7242734
    Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: July 10, 2007
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Simon J. Skierszkan, Wenbao Wang
  • Patent number: 7194059
    Abstract: A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: March 20, 2007
    Assignee: Zarlink Semiconductor, Inc.
    Inventors: Brian Wong, Benjamim Tang, Scott Southwell, Allen Sakai
  • Publication number: 20070055507
    Abstract: To reduce noise in an input signal that may contain speech, first an estimate of the noise level in the signal is obtained. The level of the input signal is then compared with the noise level estimate signal to determine whether speech is dominant. Less aggressive noise reduction is applied to the input signal when speech is dominant than when only noise is present.
    Type: Application
    Filed: August 9, 2006
    Publication date: March 8, 2007
    Applicant: Zarlink Semiconductor Inc.
    Inventors: Gary Jin, Dean Morgan
  • Publication number: 20070024383
    Abstract: The present invention is a method to rapidly lock a type II phase locked loop (PLL) after a frequency jump without degrading the output signal much. The method to decrease the settling time and improve the quality of the output clock during the settling disclosed herein comprises of the following broad steps: Estimate new frequency offset with a separate circuit outside the PLL loop to measure the frequency of the input signal accurately. Ramp integrator to the new frequency offset. Do phase build out or phase pull-in. The remaining phase offset is build out when no edge to edge alignment is required. Otherwise, the remaining phase offset is pulled in while the integrator in the PLL's loop filter is disabled. Reduce the PLL bandwidth and/or lower damping to let the PLL settle. Switch the PLL to final bandwidth and damping required by the application.
    Type: Application
    Filed: July 27, 2006
    Publication date: February 1, 2007
    Applicant: Zarlink Semiconductor Inc.
    Inventors: Menno Spijker, Jason Rosinski, Robertus van der Valk
  • Patent number: 7146003
    Abstract: A noise level calculator for detecting noise in a telephone line echo canceller that utilizes adaptive filters enables silencing of noise switching so that it is not heard on the far end side. The calculator promotes determining whether the reference signal applied to the adaptive filter is a noise or non-noise segment. The calculator operates by calculating the difference in energy of two sample windows, calculating the difference in the energy of the signal within each of the sample windows, updating a variance parameter based on the difference, and performing further alternative operations based on the value of the variance parameter.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: December 5, 2006
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Dieter Schulz, Renee Johnston
  • Publication number: 20060269029
    Abstract: A method is disclosed for recovering timing information between master and slave nodes interconnected over a packet network having an underlying time grid with a distinct granularity. A series timing packets are exchanged between said master and slave nodes to measure the time offset of the time grid relative to clocks at the master and slave clocks. This offset is then used to either adjust the local clock at the slave node, or generate the clock using a digital controlled oscillator.
    Type: Application
    Filed: April 10, 2006
    Publication date: November 30, 2006
    Applicant: Zarlink Semiconductor Inc.
    Inventors: Willem Repko, Robertus Van der Valk
  • Patent number: 7126429
    Abstract: A digital phase locked loop with fast locking capability includes a digitally controlled oscillator for producing an output signal phase locked to an input reference clock, a phase detector for measuring the phase difference between said input reference clock and a feedback clock, and a loop filter for producing a control signal for the digitally controlled oscillator The loop filter includes a proportional circuit for developing a first signal proportional to said phase difference, an integrator for developing a second integrated signal from said first signal, an adder for adding said first and second signals to develop said control signal, and a weighting circuit, preferably a linear multiplier, for selectively adding extra weight to the first signal at an input to the integrator to shorten the locking time of the phase locked loop in a fast locking mode and to rapidly achieve a stable frequency in holdover mode.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: October 24, 2006
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Krste Mitric
  • Publication number: 20060198384
    Abstract: A time division multiplex switch supporting multi-rate input and output serial data streams has a double-buffered data memory with buffer extensions associated respectively with each portion of the memory. The extensions store residual data for a delay period after the main portion of the double-buffered data memory has switched.
    Type: Application
    Filed: June 9, 2004
    Publication date: September 7, 2006
    Applicant: Zarlink Semiconductor Inc.
    Inventor: Paul Gresham
  • Patent number: 7101091
    Abstract: A device for forming an optical connection between an optoelectronic device and an optical fiber and for forming an electrical connection between the optoelectronic device and a substrate, a system including the device and materials, and methods of forming the device and system are disclosed. The device for forming an optical connection includes a—light transmission medium and electrical connectors, which are at least partially encapsulated. In addition, the device includes guide grooves configured to receive guide pins from a fiber ribbon connector, such that when the fiber ribbon connector is attached to the device, fibers of the ribbon align with the optoelectronic device via the light transmission medium.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: September 5, 2006
    Assignee: Zarlink Semiconductor, Inc.
    Inventors: Suresh Golwalkar, Noah Davis, John Burns, Kannan Raj, Phil McClay, Wuchun Chou, Jonathan McFarland
  • Patent number: 7096243
    Abstract: A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: August 22, 2006
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk
  • Patent number: 7085374
    Abstract: A distributed echo cancelling architecture is provided where echo-cancelling functions are performed at locations remote from devices receiving signals with echoes. The echo cancelling functions use a reference signal, which has been corrupted with the echoes at the devices, for echo cancellation. As echo canceller resources are located at a central system and not at each individual device, the echo canceller resources can therefore be shared between the devices.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: August 1, 2006
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Dieter Schulz
  • Patent number: 7078946
    Abstract: A resampler filter for use in an analog phase-locked loop has a charge pump and one or more switched capacitors switched by signals derived from a voltage controlled oscillator in the phase locked loop.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: July 18, 2006
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Robertus Laurentius van der Valk, Gerrit Dijkstra, Philip Ching
  • Patent number: 7010117
    Abstract: A multi-frequency tone detector with analysis window (i.e. filter size) chosen such that spectral nulls are located at adjacent frequencies of interest. The decision logic block of the tone detector uses the roll-off characteristics of the filter in conjunction with background noise to determine a threshold pass/fail for any tone that has deviated excessively from its nominal value. The foregoing aspects of the invention result in simple filter design (i.e. reduced order) relative to prior art tone detectors.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: March 7, 2006
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Dieter Schulz