Patents Assigned to Zarlink Semiconductor Inc.
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Patent number: 7006590Abstract: A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.Type: GrantFiled: May 29, 2001Date of Patent: February 28, 2006Assignee: Zarlink Semiconductor Inc.Inventors: Simon Skierszkan, Robert van der Valk
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Patent number: 7003101Abstract: A method of controlling an echo canceller in a communications channel, is disclosed wherein input signals from the communications channel are first subbanded into a subband. Echo locations are then identified within the subband and are used to control the echo canceller. Typically, the echo canceller will be a fullband echo canceller with an adaptive filter, in which case the echo locations are used to control the filter coefficients.Type: GrantFiled: August 23, 2002Date of Patent: February 21, 2006Assignee: Zarlink Semiconductor Inc.Inventor: Michael Seibert
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Patent number: 7002913Abstract: An insertion-based error concealment method and apparatus are provided whereby, instead of directly inserting white noise, a filter is created to shape the white noise. The filtered white noise is then used to replace lost data. The method of the present invention is implemented by first estimating the power spectrum of the previous frame; then designing a filter with transfer function H(f), where |H(f)|2=the estimated power spectrum; and finally generating the replacement packet using noise which has been spectrally modified by the filter. The resulting filtered noise has the same power spectrum as the previous packet but is not highly correlated with it.Type: GrantFiled: January 18, 2001Date of Patent: February 21, 2006Assignee: Zarlink Semiconductor Inc.Inventors: Ying Huang, Rafik Goubran, Dieter Schulz
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Patent number: 6999582Abstract: A method for suppressing echo signals generated in a communication path such as acoustic coupling between a speaker and a microphone in a telephone device handset includes the steps of monitoring signals supplied to the communication path to determine an attribute thereof and masking signals received from the communication path as a function of the determined attribute of the monitored signals thereby to suppress echo.Type: GrantFiled: January 20, 2000Date of Patent: February 14, 2006Assignee: Zarlink Semiconductor Inc.Inventors: Mirjana Popovic, Dieter Schulz
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Publication number: 20060023640Abstract: A methods and apparatus for remote management of switching network nodes in a stack via in-band messaging are presented. Switching nodes in the stack default to reserved switching node identifiers and stacking ports default to a blocking state upon startup, restart, and reset. Each command frame received via a blocking state is forwarded to a command engine at each switching node and is acknowledged with the current switching node identifier. Each acknowledgement frame bearing the reserved network node identifier triggers configuration of the acknowledging switching node. Switching nodes and the management processor track interrupt state vectors regarding events. An interrupt acknowledgement process is employed to track raised interrupts. Configuration of switching node is performed via command frames transmitted by the management processor and destined to a command engine associated with the switching node.Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Applicant: Zarlink Semiconductor Inc.Inventors: Rong-Feng Chang, Mike Twu, Craig Barrack, Allen Yu
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Patent number: 6985503Abstract: An inverse multiplexer device has an input port for receiving a stream of data packets, a plurality of output ports for connection to outgoing physical links, and transmit buffers for preparing outgoing packets. An expansion port can receive packets from the transmit buffers and transfer them through a corresponding expansion port on another like inverse multiplexer to designated output links on the other inverse multiplexer. A controller outputs the data packets on a group of any of the aid links in accordance with an inverse multiplex protocol. The multiplexers can be thus cascaded to increase the number of output links that can be accommodated.Type: GrantFiled: August 7, 2000Date of Patent: January 10, 2006Assignee: Zarlink Semiconductor Inc.Inventors: Marcel DeGrandpre, Alexandre Pires
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Method and apparatus providing rapid end-to-end failover in a packet switched communications network
Publication number: 20060002292Abstract: A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.Type: ApplicationFiled: July 30, 2004Publication date: January 5, 2006Applicant: Zarlink Semiconductor Inc.Inventors: Rong-Feng Chang, Eric Lin, Craig Barrack -
Combined pipelined classification and address search method and apparatus for switching environments
Publication number: 20060002386Abstract: A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Applicant: Zarlink Semiconductor Inc.Inventors: James Yik, Rong-Feng Chang, Eric Lin, John Ta, Craig Barrack -
Publication number: 20050258908Abstract: A digital phase locked loop with fast locking capability includes a digitally controlled oscillator for producing an output signal phase locked to an input reference clock, a phase detector for measuring the phase difference between said input reference clock and a feedback clock, and a loop filter for producing a control signal for the digitally controlled oscillator The loop filter includes a proportional circuit for developing a first signal proportional to said phase difference, an integrator for developing a second integrated signal from said first signal, an adder for adding said first and second signals to develop said control signal, and a weighting circuit, preferably a linear multiplier, for selectively adding extra weight to the first signal at an input to the integrator to shorten the locking time of the phase locked loop in a fast locking mode and to rapidly achieve a stable frequency in holdover mode.Type: ApplicationFiled: September 29, 2004Publication date: November 24, 2005Applicant: Zarlink Semiconductor Inc.Inventor: Krste Mitric
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Patent number: 6959064Abstract: A multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.Type: GrantFiled: December 14, 2000Date of Patent: October 25, 2005Assignee: Zarlink Semiconductor Inc.Inventors: Menno Spijker, George Jeffrey
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Patent number: 6954838Abstract: A virtual counter for dynamically calculating memory addresses at a digital switch that receives data streams of different data rates. The switch has a memory that is divisible into partitions with each partition being divisible into multiple locations. A virtual counter is implemented for each data stream in a rate conversion architecture at the switch to optimize usage of the switch memory. An input virtual counter is used to calculate a data memory address and an output virtual counter is used to calculate a connection memory address.Type: GrantFiled: May 1, 2003Date of Patent: October 11, 2005Assignee: Zarlink Semiconductor Inc.Inventors: Wenbao Wang, Kwok Fai Chan
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Publication number: 20050213571Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.Type: ApplicationFiled: March 29, 2004Publication date: September 29, 2005Applicant: Zarlink Semiconductor Inc.Inventors: Craig Barrack, Yeong Wang, Rong-Feng Chang
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Patent number: 6944288Abstract: A process is described which generates matrix coefficients using zero-lag auto and cross-correlations from signals commonly found in echo cancellers. Double-talk and path changes are then detected using matrix operations such as determinants, eigendecompositions, or singular value decompositions (SVDs). In a preferred embodiment, the determinant of the correlation-based matrix is compared against predetermined threshold values.Type: GrantFiled: January 11, 2002Date of Patent: September 13, 2005Assignee: Zarlink Semiconductor Inc.Inventor: Michael Seibert
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Patent number: 6925544Abstract: A buffer memory with a memory allocation and de-allocation circuit. The buffer memory has an address space divided into address blocks and a memory address space divided into memory blocks. The circuit, in response to an allocation request for an allocation of a certain size buffer, allocates sufficient address blocks and memory blocks for the buffer. The circuit, in response to a de-allocation request to de-allocate a certain size of memory, de-allocates whole unused address blocks and memory blocks.Type: GrantFiled: April 9, 2003Date of Patent: August 2, 2005Assignee: Zarlink Semiconductor, Inc.Inventor: Paul Gresham
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Patent number: 6920155Abstract: A circuit for measuring and compensating for propagation delays in a communication system is described. In communication systems such as wireless networks a number of base stations operate within cells to provide wide area coverage. In such systems a base station controller will communicate with each base station to provide certain information including a synchronizing time stamp. When the distance between the base station controller and each of the individual base stations is not a constant a propagation delay introduced by this distance differential will mean that the time stamp transmitted from the base station controller will not reach all the base stations at the same time. This invention relates to a system and method of measuring respective propagation delays and for introducing a compensating value.Type: GrantFiled: March 1, 2001Date of Patent: July 19, 2005Assignee: Zarlink Semiconductor, Inc.Inventor: Manjuprakash Rama Rao
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Patent number: 6882237Abstract: A voltage controlled oscillator generates an output signal whose frequency varies as a first function of a control voltage applied to a control terminal. The voltage controlled oscillator has a wide range of frequency of operation. A gain adjust circuit adjusts the gain of the voltage controlled oscillator such that the first function varies as a second function of the gain. In a preferred embodiment the gain adjust circuit includes a variable impedance that may be external or integrated onto a common chip with the oscillator core.Type: GrantFiled: April 30, 2003Date of Patent: April 19, 2005Assignee: Zarlink Semiconductor Inc.Inventors: Ranjit Singh, Youcef Fouzar, Simon John Skierszkan, Hazem Abdel-Maguid
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Publication number: 20050053076Abstract: A method of recovering timing information in a packet network is disclosed wherein a modulation scheme is used to transport additional information required for clock recovery between the sender and receiver across the network.Type: ApplicationFiled: July 21, 2003Publication date: March 10, 2005Applicant: Zarlink Semiconductor Inc.Inventors: Willem Repko, Robertus Van Der Valk, Petrus Simons, Steven Roos
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Publication number: 20050025138Abstract: A method and a TDM digital switch are provided for switching data at a variety of data rates. Input streams having a data rate less than the maximum data rate of the switch are grouped and multiplexed to form multiplexed streams carrying data at the maximum data rate. A switching state machine switches the data from each input stream to form grouped output streams comprising multiplexed output streams, each grouped output stream carrying data at the maximum data rate. The grouped output streams are demultiplexed, and the output streams transmitted through respective output shift registers. The method and TDM digital switch allow streams with programmable data rates to be switched while still maximizing use of resources, including memory, within the switch.Type: ApplicationFiled: July 13, 2004Publication date: February 3, 2005Applicant: Zarlink Semiconductor Inc.Inventor: Paul Gresham
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Publication number: 20050027768Abstract: A FIR filter for use in an adaptive multi-channel filtering system, includes a first memory for storing data, and a second memory for storing filter coefficients. The second memory stores only non-zero valued coefficients or coefficients that are above a predetermined magnitude threshold such that the overall number of coefficients processed is significantly reduced.Type: ApplicationFiled: June 14, 2004Publication date: February 3, 2005Applicant: Zarlink Semiconductor Inc.Inventor: Gord Reesor
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Publication number: 20040264477Abstract: Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points.Type: ApplicationFiled: February 18, 2004Publication date: December 30, 2004Applicant: Zarlink Semiconductor Inc.Inventors: Willem L. Repko, Robertus L. Van Der Valk, Petrus W. Simons, Craig Barrack