Abstract: A VSB modulator receives a stream of data at a 10.76 MHz constant symbol rate and converts it to a 6 MHz bandwidth signal centered at 44.0 MHz. The incoming data is interpolated by three to generate three data images and a digital filter selects the image embracing the range of 5.38 to 10.76 MHz. A sine X/X correction is added to compensate for the loss experienced in the D/A converter. The signal for the D/A converter is filtered and mixed with a 35.93 MHz oscillator output to produce data about the 44.0 MHz IF frequency. A SAW filter rejects all but the desired data.

Abstract: A technique and apparatus for developing AGC voltage in a receiver capable of receiving VSB signals that do not have the average magnitudes of the data symbol levels and the sync symbol levels related so as to produce the same average level. One technique eliminates the sync symbols from determination of the AGC voltage. A preferred technique corrects for the different symbol levels of the sync by multiplexing in an offset at the proper time or multiplying the sync symbols by a compensating factor.

Abstract: A selective RF circuit for a double conversion tuner includes three sections: low and mid band double tuned bandpass sections and a high band double tuned bandpass section. Each section includes tuning varactors and one or more coupling varactors. The varactors are operated in a first tuning mode for exhibiting a variable capacitance and in a second mode for presenting a substantial low impedance across their terminals. A microprocessor controlled circuit arrangement applies DC potentials to the tuning and coupling varactors and to two pairs of switching diodes simultaneously for selecting and tuning the desired bandpass section. The varactors in each bandpass section are complemented with fixed capacitors selected so that the product of the loaded Q and the coupling factor of any active double tuned bandpass filter is maintained substantially equal to unity over the entire tuning range.

Abstract: A remote control code translator integrated circuit converts input remote control codes of one format to output remote control codes of a different format for application to a microprocessor decoder in a television receiver. The arrangement enables a manufacturer to use common remote control codes for a number of products obtained from different OEM sources.

Abstract: A transmitted digital VSB signal comprises a sequence of M-level symbols, where the value of M is defined by a mode control signal which is periodically multiplexed with the transmitted signal. A receiver includes an up/down counter which is reset to a zero count in response to a channel change signal and a latch responsive to the zero count of the counter for storing the next received mode control signal whose accuracy has been verified. The counter is incremented or decremented in response to each subsequently received verified mode control signal which respectively matches or does not match the stored mode control signal. Acquisition of new mode control signals is thereby relatively immune to burst noise, is effected very rapidly after a channel change and less rapidly in the absence of a channel change.

Abstract: A FPLL has first second and third multipliers with the first multiplier supplying demodulated signals to a limiter and the second multiplier supplying signals to the loop filter. A VCO and phase shift circuit supply quadrature signals to the first multiplier and to the third multiplier which is relocated to an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents. The limiter output is applied to the third multiplier. The third multiplier supplies its output to the second multiplier. An integrated circuit embodiment using an exclusive OR gate as the third multiplier is also shown.

Abstract: A television chassis is arranged to receive a plug-in PIP module. When the PIP module is not installed, the composite video signal is passed through a chassis emitter follower interface circuit for video processing. The PIP module also includes an emitter follower interface circuit that supplies a composite video signal. When the PIP module is plugged in, it shares a bias resistor with the chassis emitter follower interface circuit and the PIP module interface circuit overrides the chassis interface circuit, thus passing the PIP module video signal for further video processing.

Abstract: A method and apparatus for determining network access delays in a communications network is disclosed. The communications network has a plurality of stations interconnected in a communications network. An access delay interval determining means determines a network access delay for each of the plurality of stations. That is, a time interval between a station predetermined sequence of symbols received from each of the stations and a local predetermined sequence of symbols is determined based upon a point of predetermined correlation between the station predetermined sequence of symbols and the local predetermined sequence of symbols. The time interval is used in determining the network access delay for each of the stations. The stations transmit data packets at times based upon their corresponding network access delay.

Abstract: A DC offset measurement and compensation circuit includes a switch arrangement for establishing a zero carrier condition in the circuit. The circuit output is integrated to develop any DC offsets, which are converted to analog form and subtracted from the signal output. A reference may also be subtracted to establish a base digital level for the output.

Abstract: A learning type IR function code transmitter includes a memory storing the IR function codes of a large variety of different brands of transmitters. The learning transmitter includes an IR receiver and a microprocessor for detecting IR function codes transmitted from a teaching transmitter. The memory is searched when an on/off IR function code is required from the teaching transmitter. If a match is found between the received IR function code and one of the stored IR function codes, and if a unique set of IR function codes corresponding to the identified brand of teaching transmitter IR function codes exists, the transmitter keyboard is configured to operate with the function codes that correspond to the teaching transmitter. Provision is made for teaching one or more certain IR function codes to selected keys of the learning transmitter where such certain IR function codes are not found in the memory.

Abstract: A digital receiver receives a multi level symbol signal that includes a frame sync. An equalizer is supplied with the signal and corrects for errors that are determined to exist therein on the basis of comparing the frame sync with a known value thereof or comparing the average level of the multi level symbols to an estimated (known) value thereof. A threshold circuit is included for rejecting impulse noise in the error signal that exceeds a threshold level that is higher than the maximum symbol level in the symbol.

Abstract: An adaptive equalizer decision circuit for a digital television signal, including a field synchronizing signal, consisting of multilevel symbols and a DC offset representing a pilot. The variation of the DC level of the received signal during the field sync with respect to a predetermined threshold is derived for placing the equalizer in a training signal or data directed operating mode. Another approach determines the difference between a current value of the field sync and each of a plurality of values of the field sync in previous fields and determining therefrom whether the equalizer should be in its data directed mode of operation or in its training signal mode of operation. A modification consists in controlling the step size of the equalizer based upon either the DC level variation or the field sync differences of the received signal. The modification may be used alone or in combination with the equalizer operating mode control.

Abstract: A remote control transmitter has a kill mode in which less power is drawn than in the full power operating mode. The transmitter has a stop mode in which minimal power is consumed. The stop mode is entered whenever no keys are being depressed. The device stays in the kill mode whenever a key closure is maintained for longer than a predetermined time.

Abstract: A subscriber terminal includes a digital conditional access module receiving a transport bitstream comprising a plurality of multiplexed conditional access and product packets. Selected ones of the conditional access packets are addressed to respective terminals and include an encrypted new decryption key code, an encrypted authorization bit map and an authorization list range delete code. The conditional access packets are decrypted by the conditional access modules of respective addressed terminals, the decrypted new decryption key code being stored for subsequent use by the conditional access module, the decrypted authorization bit map being used to refresh the authorization bit map memory of the module and the decrypted delete code being used to delete a specified range of authorization codes from the authorization list memory of the module.

Abstract: A data frame structure for a digital information signal comprises a first fixed number of repetitive data segments each containing a second fixed number of M-level symbols representing a plurality of data bytes and a data segment sync character. The frame further includes a header segment including a frame sync code and a mode code defining the value of M for the data frame. The data frame incorporates error correction blocks and is configured to provide an integral number of data bytes and error correction blocks for each of a plurality of different values of M.

Abstract: A polarity detection circuit for an FPLL demodulated signal including a small DC pilot recovers the DC pilot by determining the DC levels of the demodulated output signals both with and without the DC pilot. A zero carrier condition is created for determining the DC level of the output signal without the DC pilot. The two DC levels are subtracted and limited and the polarity of the recovered DC pilot is used to control the operation of a polarity inverter to assure that the output signal has a desired polarity.

Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock indicator circuit determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming signal (or alternatively, of the outgoing signal) as determined in order to supply an output signal of predetermined polarity. The frequency lock indicator consists of a zero crossings detector and a latch that is sampled for a time period. The zero crossings detector is a delay and an exclusive OR gate. An optional confidence counter may be used with the latch to determine when frequency lock has occurred to provide the lock indicator signal.

Abstract: A method for use in the construction of a color display screen using deposition of a plurality of electroluminescent materials onto a substrate bearing said screen. The method comprises the forming operations a), b), and c) in any sequence: a) forming on the substrate a first pattern of deposition sites covered with a first material selectively strippable by a first agent; b) forming on the substrate a second pattern of deposition sites covered with a second material strippable by a second agent but not significantly attacked by said first agent; and c) forming on the substrate a matrix surrounding the first and second patterns of deposition sites. The method includes thereafter performing a first stripping of the first material with the first agent to reveal first deposition sites within the matrix and performing a first depositing of a first electroluminescent material within the first revealed deposition sites.