Patents Examined by A. A. Turner
  • Patent number: 11908913
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the drain contact or the source contact includes a conductive material, such as ruthenium, to reduce the Schottky effects at the interface with the channel material.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi, Scott E. Sills
  • Patent number: 11890622
    Abstract: A wearable air purifier includes at least one wearable component, a control unit, at least one speaker assembly and at least one negative ion generating component. The control unit is disposed inside the at least one wearable component. The at least one speaker assembly is disposed on the at least one wearable component and electrically connected to the control unit. The at least one negative ion generating component is disposed on the at least one wearable component and electrically connected to the control unit. The control unit provides high-voltage currents to the at least one negative ion generating component to enable the at least one negative ion generating component to emit negative ions by corona discharging, and the control unit further provides audio signals to the at least one speaker assembly to activate the at least one speaker assembly to generate sound.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: February 6, 2024
    Assignee: ible Technology Inc.
    Inventors: Hung-Hsuan Chien, Yu-Fan Tsai
  • Patent number: 11889847
    Abstract: The present invention relates to a method for producing a coffee extract which comprises use of an enzyme having ?-1,3-galactanase activity and to a coffee extract which comprises at least 20% based on the total weight of soluble coffee solids of total galactose.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: February 6, 2024
    Assignee: Novozymes A/S
    Inventors: Nikolaj Spodsberg, Kristian Bertel Roemer M Krogh, Rune Nygaard Monrad, Jens Ekloef, Louise Rasmussen, Gitte Budolfsen Lynglev, Laure Coulomb
  • Patent number: 11887138
    Abstract: A computer system and computer-implemented method for retail merchandise planning, including promotional product selection, price optimization and planning. According to one or more embodiments, the computer system for generating an electronic retail plan for a retailer comprises, a data staging module configured to input retail sensory data from one or more computer systems associated with the retailer; a data processing module configured to pre-process the inputted retail sensory data; a data warehouse module configured to store the inputted retail sensory data and the pre-processed retail sensory data; a state model module configured to generate a retailer state model for modeling operation of the retailer based on the retail sensory data; a calibration module configured to calibrate the state model module according to one or more control parameters; and an output module for generating an electronic retail plan for the retailer based on the retailer state model.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: January 30, 2024
    Assignee: Daisy Intelligence Corporation
    Inventor: Kari Saarenvirta
  • Patent number: 11889704
    Abstract: A device includes gate-all-around transistors and method for manufacturing such a device. A method for manufacturing a microelectronic device includes at least two transistors each comprising a channel in the shape of a wire extending in a first direction x, a gate surrounding said channel, a source and a drain, said transistors being stacked in a third direction z and each occupying a level nz (z=1 . . . 4) of given altitude in the third direction z.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: January 30, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, François Andrieu
  • Patent number: 11884852
    Abstract: The present invention is to provide multilayered multiple quantum dot-doped nanoparticles, each of the multiple quantum dot-doped nanoparticles has a structure consisting of an inorganic core particle, a quantum dot-embedded layer, and a silica/quantum dot composite shell. The multiple quantum dot-doped nanoparticles can be used to detect biomolecules with improved quantum yield (QY) and brightness while maintaining a large area covered by the quantum dots and stable bonds of the quantum dots. Therefore, the multiple quantum dot-doped nanoparticles are suitable for bioapplications, including bioplatforms and highly sensitive methods for detecting biomolecules.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 30, 2024
    Assignees: BIOSQUARE INC., KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP
    Inventors: Bong Hyun Jun, Sung Wook Yoon, Yoon Sik Lee, Dong Ok Choi, Xuan Hung Pham, Tae Han Kim, Jung Won Kim
  • Patent number: 11875294
    Abstract: A method to provide multi-objective recommendations. The method includes receiving user input indicating a plurality of objectives, where each of the plurality of objectives indicates a desired goal for a field of interest, receiving user input indicating a plurality of actionable fields, receiving user input indicating selection of one of a plurality of records in a data set, determining, based on applying an evolutionary algorithm, one or more candidate changes to values of the plurality of actionable fields of the selected record, determining, for each of the one or more candidate changes, a multi-objective score for that candidate change, selecting one or more of the one or more candidate changes to recommend to a user based on the multi-objective scores of the one or more candidate changes, and providing, for display to the user, the selected one or more candidate changes as recommended changes.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: January 16, 2024
    Assignee: Salesforce, Inc.
    Inventors: Lingtao Zhang, Chang Lu, Sybil Shim, Amit Kumar
  • Patent number: 11866203
    Abstract: Systems and methods to remove dust from an extravehicular mobility unit (EMU) worn by an astronaut in a deep space environment involve one or more ionic shower units installed external to an interior volume of a facility. Each ionic shower unit releases positively charged ions and negatively charged ions in a specified direction to neutralize the dust and generate neutralized dust. The interior volume of the facility is defined by an interior hatch that is separated from an exterior hatch by an airlock. One or more collection units is installed external to the interior volume. Each collection unit traps the neutralized dust to prevent the dust from entering the interior volume.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 9, 2024
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventors: Julie Strickland, Nicholas Brophy
  • Patent number: 11865551
    Abstract: Provided are purification systems and methods of using such systems for purifying various environments, such as indoor air, outdoor air, vehicle emissions, and industrial emissions. A purification system comprises an ionizing purifier having a substrate and an active coating. The active coating comprises a pyroelectric and/or piezoelectric material. During the operation, an incoming stream is directed toward the active coating while controlling the average pressure exerting on the active coating. This contact between the incoming stream and the active coating generates negative ions from components of the incoming stream via change in temperature and pressure/force/vibration, etc. The negative ions then interact with pollutants, transforming them into safe, purified materials of the outgoing stream. Unlike the pollutants in the incoming stream, the purified materials are non-harmful, and/or can be easily removed from the outgoing stream, e.g., by filtering and/or other separation techniques.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: January 9, 2024
    Assignee: Rainlons Corp.
    Inventor: Mark DiCarlo
  • Patent number: 11862561
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11862622
    Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Chien-Hung Chen, Chun-Hsien Lin
  • Patent number: 11862465
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Patent number: 11862700
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Chun-Fu Lu, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11854791
    Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Pei-Yu Wang
  • Patent number: 11855225
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Yeh Chen, Wei-Yang Lee, Chia-Pin Lin
  • Patent number: 11855143
    Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11854892
    Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: December 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Yoon, Jungchul Lee, Byungmoon Bae, Junggeun Shin, Hyunsu Sim
  • Patent number: RE49774
    Abstract: The invention relates to methods for conducting solid-phase binding assays. One example is an assay method having improved analyte specificity where specificity is limited by the presence of non-specific binding interactions.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: January 2, 2024
    Assignee: MESO SCALE TECHNOLOGIES, LLC.
    Inventors: Eli N. Glezer, Sudeep Kumar, Pankaj Oberoi, George Sigal, Michael Tsionsky
  • Patent number: RE49816
    Abstract: The compounds of the present invention are represented by the following compounds having Formula (I) where the substituents R1-R10, X, Y, k, m, n, q, and s are as defined herein. These compounds are used in the treatment of cancer, immunologic disorders, autoimmune disorders, neurodegenerative disorders, or inflammatory disorders or for providing immunosuppression for transplanted organs or tissues.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: January 30, 2024
    Assignee: CORNELL UNIVERSITY
    Inventors: Gang Lin, Carl Nathan, Aihao Ding, Xiaojing Ma
  • Patent number: RE49835
    Abstract: A multiplex polymerase chain reaction assay that targets nine tetranucleotide short tandem repeat (STR) markers in the mouse genome. Unique profiles were obtained from seventy-two mouse samples that were used to determine the allele distribution for each STR marker. Correlations between allele fragment length and repeat number were determined with DNA Sanger sequencing. Genotypes for L929 and NIH3T3 cell lines were shown to be stable with increasing passage numbers as there were no significant differences in fragment length with samples of low passage when compared to high passage samples. In order to detect cell line contaminants, primers for two human STR markers were incorporated into the multiplex assay to facilitate detection of human and African green monkey DNA. This multiplex assay is the first of its kind to provide a unique STR profile for each individual mouse sample and can be used to authenticate mouse cell lines.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: February 13, 2024
    Assignee: United States of America as Represented by the Secretary of Commerce
    Inventors: Jamie L Almeida, Kenneth D. Cole