Abstract: The semiconductor device includes a semiconductor element having first and second main electrodes, first and second substrates connected to the first and second main electrodes, respectively, first and second main terminals connected to the first and second main electrodes via the first and second substrates, respectively, and a bonding member. The bonding member is interposed between the first and second main electrodes and between the first and second substrates, respectively. At least one of the first and second main terminals includes a plurality of terminals. The first and second main terminals are alternately arranged in one direction orthogonal to the thickness direction of the semiconductor element. The first and second main terminals are directly bonded to the first and second substrates without the bonding member.

Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

Abstract: A gate driver includes signal transmission units cascade-connected via a carry line to which a carry signal is applied from a previous signal transmission unit. An nth signal transmission unit includes: a first circuit including a first Q logic generator to receive the carry signal from the previous signal transmission unit to charge a first control node, and a second Q logic generator to discharge the first control node; a second circuit to discharge a second control node according to a first control node voltage; and an output to output the carry signal and a gate signal based on potentials of the first and second control nodes. The second Q logic generator includes: a second-1 transistor and a second-2 transistor each respectively having a first electrode, a gate electrode, a back gate electrode, and a second electrode.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.

Abstract: A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.

Abstract: A method for preparing method semiconductor device includes: providing a wafer on which a semiconductor structure is formed; forming a stacked film layer structure on a side of the semiconductor structure away from the wafer, a film layer in the stacked film layer structure farthest from the semiconductor structure being a first film layer; reducing a thickness of the first film layer so that the thickness of the first film layer at where orthographic projection of the first film layer on the wafer locates at an edge of the wafer is less than the thickness of the first film layer at where orthographic projection of the first film layer on the wafer locates in middle of the wafer; and patterning the stacked film layer structure to form through holes which communicate to the semiconductor structure.

Abstract: An information processing device includes an acquisition unit and an association unit. The acquisition unit is configured to acquire first information which is generated by processing a detection result output from a first sensor provided outside of a plurality of electronic writing tools with which a plurality of objects are drawn on a display image and includes positions at which the plurality of electronic writing tools are detected on the display image and acquiring second information which is generated by processing a detection result output from a second sensor provided in each of the plurality of electronic writing tools and includes relative positions of the other electronic writing tools relative to each electronic writing tool. The association unit is configured to associate the plurality of electronic writing tools with positions of the plurality of electronic writing tools on the display image, respectively, using the first information and the second information.

Abstract: A display device comprises a display substrate, first interconnections, second interconnections, a driving circuit and a polarizing plate. The display substrate includes a bend portion which is curved with respect to an axis parallel to a first direction. The first interconnections extend in the first direction and are on the display substrate. The second interconnections are on the display substrate, connected to the first interconnections and extend in a second direction different from the first direction. The driving circuit is electrically connected to the first interconnections and the second interconnections and provides driving signals to the first interconnections and the second interconnections. The polarizing plate is on the display substrate and overlaps the first interconnections and the second interconnections.

Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

Abstract: Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Abstract: A device is configured to provide performance support in a low-gravity environment. The device obtains and operates on first data indicative of a body pose of an individual, and second data indicative of a gaze direction of the individual. The device is configured to determine, based on the first data and the second data, a first time series of body poses and a second time series of gaze directions that represent the individual performing a task, obtain a nominal performance scheme for the task, perform an evaluation of the first and second time series in relation to the nominal performance scheme for detection of a performance deviation, and provide, based on the evaluation, feedback data for presentation by a feedback device.

Abstract: An electronic reader is implemented in a mobile computing device by downloading electronic reader computer instructions to be stored resident in the mobile computing device to permit the mobile computing device to be configured as a stand-alone electronic reader. One or more electronic books are downloaded and temporarily stored in a memory of the electronic reader. Chatroom functionality is integrated into the electronic reader to permit a user to communicate directly from an electronic book to a chatroom to thereby permit communication with selected parties. The user can communicate with other readers in the chatroom, with the author of the book, or with one or more subject matter experts designated by the author or publisher of the book. The integrated chatroom functionality combined with the stand-alone reader functionality provide a quality reading experience for the user as well as interactive capabilities.

Abstract: One or more environmental vibrations that originate from a vibration source are detected by a wearable display device. The wearable display device is worn by a user. The vibration source is located in an environment that is proximate to the wearable display device. An alert condition related to the vibration source is identified, based on the one or more environmental vibrations. An augmented notification for the wearable display device is generated in response to the alert condition. The augmented notification provided, by the wearable display device, to the user.

Abstract: When a notification is to be shown, an artificial reality notification system can add the notification to a pre-defined location in the user's field of view (e.g., top, side, or bottom) where it stays as a head leashed virtual object until the user's gaze is direct to the notification. When the user's gaze is directed at the notification, the artificial reality notification system make the notification world locked, allowing the user to move her head to bring the notification to the center of her field of view, move closer to the notification to make it larger, move around the notification to see aspects from different angles, etc. The notification can be dismissed if the user never directs her gaze at it for a first threshold amount of time or when the user looks away from the world-locked version for a second threshold amount of time.

Abstract: Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOT FETs and fully depleted SOI FETs may be provided.

Abstract: An integrated circuit is disclosed. The integrated circuit includes conductive rails, signal rails, at least one first via, and at least one first conductive segment. The at least one first via is disposed between the first conductive layer and the second conductive layer, and couples a first signal rail of the signal rails to at least one of the conductive rails. The first signal rail is configured to transmit a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first conductive segment is disposed between the first conductive layer and the second conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.